Dimiter R. Avresky

Performance evaluation of the ServerNet(R) SAN under self-similar traffic

Self-similar traffic distributions have been observed in a wide range of networking applications and models such as LANs, WANs, telnet, FTP, WWW, ISDN, SS7 and VBR traffic over ATM. Therefore, it has been suggested that many other theoretical protocols and systems need to be reevaluated under this different type of traffic before practical implementations potentially show their faults. The ServerNet SAN is a new core technology for server architectures that focuses on moving data. It is a wormhole-routed, packet-switched, point-to-point network with special attention paid to reducing latency and assuring reliability. In this paper we investigate the implications of self-similar traffic distributions in the ServerNet SAN, and compare the results with those obtained on the basis of the Poisson assumption.

On the covering of vertices for fault diagnosis in hypercubes

Abstract We investigate the optimal covering of vertices by Hamming balls of radius t in a hypercube Z2n such that any vertex in Z2n can be uniquely identified by examining the vertices that cover it. Given Z2n and an integer t ⩾ 1, we find a (minimal) set C of vertices such that every vertex in Z2n belongs to a unique set of balls of radius t centered at the vertices in C . This is useful in diagnosing processor faults in hypercube-based multiprocessor systems.

Performance modeling of ServerNet topologies

This paper describes a performance analysis of ServerNet SAN, a new system area network architecture developed by Tandem Computers. The paper focuses on three main topics: a brief description of the ServerNet SAN architecture and the simulation tool, the basis for modeling assumptions, and the initial results of the performance and scalability analysis. The ServerNet SAN is a new core technology for server architectures that focuses on moving data. The analysis uses simulation to obtain performance characteristics such as delivery time, throughput, and hot spot identification. The goal of the analysis is to provide a realistic measure of current system performance, while optimizing features such as network topology and traffic patterns to provide future improvement.

Message routing in 3D networks-on-chip

Nowadays 3D chips are fabricated by stacking 2D layers and manufacturing vertical links between them. In this paper we present a routing scheme suited for 3D networks-on-chip (NoCs). It is based on the reuse of existing routing schemes for 2D NoCs. Our 3D scheme is scalable and can be used with any 2D topology. The effectiveness of the scheme for intra-layer communication is given by the respective 2D routing scheme of each layer, while for the inter-layer communication the scheme can always find a route between any source and destination, if there is one available.

Embedding and reconfiguration of spanning trees in faulty hypercubes

The problem of tolerating faulty nodes in hypercubes has been studied by many researchers either by using spares or by reconfiguration. Algorithms for tolerating faulty nodes and links in hypercubes are presented. The algorithms are based on using general spanning trees (GST), complete unbalanced spanning trees (CUST), and balanced spanning trees (BST) for reconfiguring the hypercube to avoid faulty nodes and links. The algorithms contain two phases: the first phase involves the construction of the spanning tree and the second one is for reconfiguring the hypercube should a faulty node be detected. The reconfiguration process consists of two basic steps. First, the faulty node is disconnected from the spanning tree. Then, a new spanning tree is constructed by reconnecting the children of the faulty node to the spanning tree. One hundred percent single fault correction (avoidance) and almost 100 percent fault correction (avoidance) of double and triple faults are achieved by the proposed algorithms for hypercubes having a dimension of n/spl ges/6. Simulation results for the algorithm under more than three faults also are presented. For any k faulty nodes (1/spl les/k/spl les/2/sup n/-1), the reconfiguration algorithm may be applied k times to avoid these k faulty nodes as long as no combination of any two of the faults results in a blocking situation. The proposed reconfiguration algorithms tolerate all possible single-link faults. The reconfiguration algorithms are extended to tolerate (k/spl les/n-1) multiple faults, causing blocking situation, with a backtracking.

Design for test and reliability in ultimate CMOS

This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14 nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of single-chip massively parallel tera-device processors could comprise timing faults (such as delay faults or clock skews); a large percentage of these parts are affected by catastrophic failures; all parts experience significant performance degradations over time; and new catastrophic failures occur at low MTBF.

The effect of the router arbitration policy on the scalability of ServerNet™ topologies

Abstract Multistage networks are finding increasing use in building clusters of workstations and PCs. The networks that support such connectivity must provide high bandwidth, low latency, scalability, low cost, high level of usability, and reliability [1]. A key parameter that influences the network performance characteristics such as maximum latency, throughput, scalability and tree saturation, is the arbitration policy implemented in routers.

Adaptive inter-layer message routing in 3D networks-on-chip

Existing routing algorithms for 3D deal with regular mesh/torus 3D topologies. Today 3D NoCs are quite irregular, especially those with heterogeneous layers. In this paper, we present a routing algorithm targeting 3D networks-on-chip (NoCs) with incomplete sets of vertical links between adjacent layers. The routing algorithm tolerates multiple link and node failures, in the case of absence of NoC partitioning. In addition, it deals with congestion. The routing algorithm for 3D NoCs preserves the deadlock-free propriety of the chosen 2D routing algorithms. It is also scalable and supports a local reconfiguration that complements the reconfiguration of the 2D routing algorithms in case of failures of nodes or links. The algorithm incurs a small overhead in terms of exchanged messages for reconfiguration and does not introduce significant additional complexity in the routers. Theoretical analysis of the 3D routing algorithm is provided and validated by simulations for different traffic loads and failure rates.

RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip

In the context of the emerging 3D integration paradigm, chips are built as stacks of several (likely heterogeneous) 2D layers. The topology of their communication network is quite irregular, mainly due to the different topologies of the 2D layers and the partial vertical connection between these layers. In this paper, a reconfigurable inter-layer routing mechanism (RILM) for such topologies is proposed. We firstly present the mechanism of composing the routing algorithms in different layers, through the vertical links, in order to achieve a multi-layer routing algorithm. Reconfiguration of the routing can be done for multiple reasons: to achieve fault-tolerant capability, but also under dynamic changing of the communication requirements, or, simply, to avoid congestions. To obtain a complete routing reconfiguration for the entire stack of layers, we propose a reconfiguration algorithm of the inter-layer routes, as a complement to the 2D routing reconfiguration. Additionally, independently of the 2D routing algorithm properties, RILM tolerates multiple failures of vertical links, as long as the stack of layers is not partitioned.

Formal verification and testing of protocols

We adopt a formalism to describe protocols that is close to the human way of thinking and can be easily used to perform reachability analysis of the described protocol in a state-transition format. This formalism allows for an execution tree (ET) to be generated from a set of assertions such that all paths from the root to the leaves are well-defined formulas. We then extend the formalism with regards to real-time properties. Finally, we present a software verification tool, that implements the aforementioned features in the analysis of protocols.