Dinesh Koli

FinFET performance advantage at 22nm: An AC perspective

At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

High performance bulk planar 20nm CMOS technology for low power mobile applications

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

Microreplicated CMP pad for RMG and MOL metallization

Microreplicated CMP pad is applied to W and Co buff CMP steps for topography and WiDNU reduction of RMG and MOL metallization. This new pad exhibits stable rates and low defectivity over extended life time without the need for diamond conditioner. It also demonstrates reduction in topography built-up at device level and die level, leading to remarkable reduction in topo-related defects for MOL local interconnects.

Study of sol-gel type ceria particle for CMP process in leading-edge CMOS device

With continuous shrink in the size of integrated circuits, the complexity, and the number of processing steps continue to increase. CMP is one of the crucial steps to maintain good process yields. The number of FEOL CMP steps has increased drastically in leading-edge nodes and also made the process requirements more stringent. In order to meet these requirements, selection of the right consumables is very critical. Slurry plays a vital role in CMP processes and there is always a big requirement for extreme selective slurry with self-stopping capabilities. Also, the final CMP surface should be very smooth with no defects and scratch free. Ceria-based slurries are gaining importance as they have good planarization and self-stopping capabilities in the latest device technology. In this paper, we have investigated some of the notable ceria types such as composite ceria, calcined ceria and wet ceria. The particle hardness of wet ceria is 1/25th level compare to other ceria particles. This helps the surface be defect and scratch-free. In our experiment, 60% reduction in surface roughness and 90% reduction in scratches on patterned wafers was observed.

SiOC CMP developed and implemented in 7nm and beyond

In this study, new SiOC Chemical Mechanical Planarization (CMP) process is fully developed with the characterization of the blanket wafer selectivity, SiN loss on pattern wafer, within chip SiN uniformity, and topography of CMP house and device areas using Atomic-force microscopy (AFM), Transmission electron microscopy (TEM), high resolution profiler (HRP) and KLA-Aleris. Those results of SiN within-chip uniformity show one step process (only slurry A_bulk + SiN stop) with poor process window, which cannot meet 7nm MOL integration process requirement. And two steps process (Slurry A_bulk + Slurry B_SiN stop) with promising results, good SiN within-chip uniformity (< 2nm) and wide process overpolish margin.

Challenges in Chemical Mechanical Planarization defects of 7nm device and its improvement opportunities

CMP (Chemical Mechanical Planarization) defects are always one of the top yield detractors in IC (Integrated Circuit) devices since CMP processes have been applied in the semiconductor industry. Most of all, new structures and materials in 7nm devices make it challenging for CMP processes to meet device requirements. The CMP process obviously needs to control or contain not only the number of defects but also defect size in accordance with scaling speed. In this paper, the results of fundamental studies to elucidate CMP defects will be introduced and discussed as they pertain to 7nm devices. This paper will cover the phenomena and its research activities about atomic scale scratches, dishing control in uneven surface topography and surface defects with 7 nm logic device.

20nm CMP model calibration with optimized metrology data and CMP model applications

Chemical Mechanical Polishing (CMP) is the essential process for planarization of wafer surface in semiconductor manufacturing. CMP process helps to produce smaller ICs with more electronic circuits improving chip speed and performance. CMP also helps to increase throughput and yield, which results in reduction of IC manufacturer’s total production costs. CMP simulation model will help to early predict CMP manufacturing hotspots and minimize the CMP and CMP induced Lithography and Etch defects [2]. In the advanced process nodes, conventional dummy fill insertion for uniform density is not able to address all the CMP short-range, long-range, multi-layer stacking and other effects like pad conditioning, slurry selectivity, etc. In this paper, we present the flow for 20nm CMP modeling using Mentor Graphics CMP modeling tools to build a multilayer Cu-CMP model and study hotspots. We present the inputs required for good CMP model calibration, challenges faced with metrology collections and techniques to optimize the wafer cost. We showcase the CMP model validation results and the model applications to predict multilayer topography accumulation affects for hotspot detection. We provide the flow for early detection of CMP hotspots with Calibre CMPAnalyzer to improve Design-for-Manufacturability (DFM) robustness.