Dinesh Ramanathan

System level online power management algorithms

The problem of power management for an embedded system is to reduce system level power dissipation by shutting off parts of the system when they are not being used and turning them back on when they are required. Algorithms for this problem are online in nature where the algorithm must operate without access to the complete data set or its characteristics. In this paper, we present online algorithms to manage power for embedded systems and provide experimental analysis to back up the theoretical results. Specifically, this paper makes four contributions. We propose an optimal online algorithm for power management. We present an analysis of algorithmic efficiency using a technique called competitive analysis which is particularly suitable for online algorithms. Using this analysis technique, we develop a lower bound for the non-adaptive version of the power management problem and show that our algorithm achieves this lower bound. Next, we explore adaptive algorithms that try to shut down the system based on historical data. We provide a lower bound for any algorithm that uses adaptive methods to manage power. We also propose an algorithm that is independent of the input data distribution, practical and usable in both hardware and software systems with guaranteed performance. Finally, we compare these algorithms with previously proposed heuristics both theoretically and experimentally. For the experiments, we model the disk drive of a laptop computer as an embedded system. The results show that the proposed algorithms perform well in practice with guaranteed bounds on their performance. Further, this paper conclusively demonstrates that to implement aggressive power management techniques for power critical subsystems, designers will have to commit greater resources such as dedicated registers and ALU units.

An analysis of system level power management algorithms and their effects on latency

The problem of power management for an embedded system is to reduce system level power dissipation by shutting off parts of the system when they are not being used and turning them back on when requests have to be serviced. Algorithms for this problem are online in nature; the algorithm must operate only with access to data that it has seen so far and without access to the complete data set or its characteristics. We present online algorithms to manage power for embedded systems and discuss their effects on system latency. We introduce competitive analysis as a formal framework for the evaluation of various power management algorithms. Competitive analysis does not depend on the distribution of interarrival times of requests. We present a nonadaptive online algorithm, analyze its behavior, and show that it is optimal. We also present a lower bound on the competitiveness of any adaptive algorithm. We show that no adaptive online algorithm can dissipate less than about 1.6 times the power dissipated by the optimal offline algorithm in the worst case. We also show that in order for any online algorithm to achieve this lower bound, it may have to maintain a complete history of the interarrival. times of the requests in the input sequence. Since this is not practical, we present a simple algorithm that uses only the last interarrival time to predict the arrival of the next request.

Interfacing hardware and software using C++ class libraries

As chip capacity increases and system-on-a-chip becomes more than just a catch phrase, hardware and system design are being driven in new directions. Systems are designed not just as hardware, but as a tightly coupled combination of both hardware and software. C++, extended with class libraries, is emerging as the way to design such complex systems. This paper proposes methods to specify and refine designs from a purely software description at a functional level to a level where the hardware components are encapsulated as objects and their interfaces clearly defined. The entire system functionality is described in C++ using some of the commercially available class libraries like SystemC from Synopsys and Cynlib from CynApps. We propose a methodology where a designer can migrate software functionality. We also show that the software driver for the hardware device is generated as a side-effect of the interface refinement process. We demonstrate our methodology on the design of a fax machine from a purely software description of the system. We refine the design by implementing its decoder functionality in hardware and interfacing it with the software encoder.

Timing-driven HW/SW codesign based on task structuring and process timing simulation

Task structuring is the process of determining the individual tasks of a system, leading to the systems description as a task graph. This paper shows that RADHA-RATAN, our rate derivation algorithms, can be used to validate various tradeoffs made during task structuring, making this step timing aware. We show how RADHA-RATAN enables construction of a high-level timing model of the system leading to a process timing simulation of the entire system. An interesting aspect of process timing simulation is that it provides the ability to observe system level timing behavior based on timing requirements and analysis before an implementation of the tasks has been carried out. Based on task structuring and process timing simulation we propose a codesign methodology by which a system designer can gain insight into the systems timing performance. This approach enables the designer to reduce expensive timing driven design iterations. We have implemented this methodology in the RADHA-RATAN framework. We illustrate its application by an example.

Timing driven co-design of networked embedded systems

Advances in microelectronics integration have led to the emergence of tightly integrated systems with high performance network interfaces. Design of such systems especially for single chip implementation is a delicate balance of functionality and available time budget to perform the tasks. Computer-aided design tools and methodologies are needed to ensure the correctness of the design and efficiency of the design process, especially for networked systems that have strict timing requirements both due to technology as well as networking needs. We present an overview of a timing-driven design methodology for networked systems, developed at the University of California, Irvine.