Dirk M. Baars
Rogers Corporation
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Featured researches published by Dirk M. Baars.
electronic components and technology conference | 2010
Fuhan Liu; Venky Sundaram; Sunghwan Min; Vivek Sridharan; Hunter Chan; Nitesh Kumbhat; Baik-Woo Lee; Rao Tummala; Dirk M. Baars; Scott Kennedy; Sankar Paul
This paper presents for the first time a novel manufacturing-compatible organic substrate and interconnect technology using ultra-thin chip-last embedded active and passive components for digital, analog, MEMS, RF, microwave and millimeter wave applications. The architecture of the platform consists of a low-CTE thin core and minimum number of thin build up organic dielectric and conductive layers. This organic substrate is based on a new generation of low-loss and thermally-stable thermosetting polymers (RXP-1 and RXP-4). Unlike LCP- and Teflon-based materials, the RXP material system is fully compatible with conventional FR-4 manufacturing processes. Ultra-thin silicon test die (55µm thick) has been embedded in a 60µm deep cavity with a 6-metal layer RXP substrate and a total thickness of 0.22mm. The embedded IC is interconnected to the substrate by ultra-fine pitch Cu-to-Cu bonding with polymer adhesives. This novel interconnection process performed at 180°C, has passed 1,000 thermal shock cycles in reliability testing. Because of manufacturing process simplicity and unparalleled set of benefits, the chip-last technology described in this paper provides the benefits of chip-first without its disadvantages and thus enables highly miniaturized, multi-band, high performance 3D modules by stacking embedded 3D ICs or packages with embedded actives, passives and MEMS devices.
electronic components and technology conference | 2009
Fuhan Liu; Venky Sundaram; Hunter Chan; Ganesh Krishnan; Jintang Shang; John Dobrick; Jack Neill; Dirk M. Baars; Scott Kennedy; Rao Tummala
In this paper we present an ultra-high wiring density build-up substrate targeted at 30µm IC-to-substrate interconnect pitch, using a new low loss thin core laminate (RXP-1) and low dielectric constant and low loss thin build up dielectric (RXP-4). The RXP-1 core is a glass fiber reinforced organic laminate with a thickness in the range of 50–110µm. The RXP-1 core has a stable dielectric constant of 3.25 and loss tangent of 0.004 at 1–40GHz. The RXP-4 build-up film has a stable dielectric constant ≪3, a loss tangent of 0.004 at 1–40GHz [1] and a film thickness of 10–25µm. A process test vehicle having a 4-metal layers structure (1+2+1) was designed for process development and reliability characterization. The total thickness of the completed 4-metal layer substrate demonstrated was 160µm. The substrate design rules include a minimum copper line width and space of 15µm, blind microvia diameter of 25µm and through hole diameter of 50µm. Line width and space of 10µm and through hole diameter of 30µm was also designed for testing the process limits. Preconditioning test, 3X lead-free reflow and thermal shock (−55∼+125°C, air-to-air) test up to 1,400 cycles showed that the new low loss thin dielectric film and thin core organic system is reliable. This substrate can be used for high speed systems, low profile thin packages, portable devices, mobile applications, system-in-package (SiP) and system-on-package (SOP).
IEEE Transactions on Advanced Packaging | 2010
Seunghyun Hwang; Sunghwan Min; Madhavan Swaminathan; Venkatesan Venkatakrishnan; Hunter Chan; Fuhan Liu; Venky Sundaram; Scott Kennedy; Dirk M. Baars; Benjamin Lacroix; Yuan Li; John Papapolymerou
This paper presents, for the first time, characterization results of next generation dielectric core and build up material called RXP, which has low dielectric constant (2.93-3.48) and low loss tangent (0.0037-0.006) up to 110 GHz. Unlike LCP, this material can be made ultra-thin with low processing temperature and is ideally suited for mobile applications. Causal models suitable for high frequency applications have been extracted by measuring the response of cavity resonators using vector network analyzer and surface profiler.
IEEE Transactions on Components, Packaging and Manufacturing Technology | 2012
Baik-Woo Lee; Venky Sundaram; Scott Kennedy; Dirk M. Baars; Rao Tummala
Embedded actives are to bury thinned active chips into package substrates, as opposed to surface mounted devices (SMDs), which can achieve smaller form factor, better electrical performance and higher functionality than the SMD technology. While many embedded actives have been explored so far, they are based on chip-first and -middle approaches, in which the active chips are embedded before and during the build-up processes of package substrates, respectively. The most concern with those two current approaches is the loss accumulation associated with the build-up layer processes carried out right on top of the embedded chips, which is highly likely to lose the embedded chips during their packaging process. The reworkability to replace the faulty chips embedded with good ones and thermal management of the embedded chips are also issues since the embedded chips are totally surrounded by hard-cured polymers. In this paper, chip-last embedded active has been proposed to address some of the issues that are reported in current chip-first and -middle approaches, in which chips are embedded after all the package substrate processes including the build-up layers are completed, just like conventional SMD packaging. In the chip-last approach, a cavity is introduced within the build-up layers of package substrate and a chip is directly embedded into the cavity. A first proto-type of the chip-last embedded active will be demonstrated by developing various cavity formation processes within the build-up layers and then embedding 100 μm thick chips into the defined cavities.
electronic components and technology conference | 2008
Ganesh Krishnan; Fuhan Liu; Venky Sundaram; Raghuram V. Pucha; Scott Kennedy; Dirk M. Baars; John Dobrick; David Guo; Jack Neill; Sankar Paul; Rao Tummala
This paper introduces a new developmental family of thin film dielectric materials that have low dielectric constant (2.5 - 3.1 ) and low loss tangent (<0.005) at 10 GHz and discusses process development and reliability testing of a 1-2-1 substrate stack-up with versions of these high-performance developmental dielectrics (RXP-4). The variant used in these experiments is called RXP-4a. Various conditions were tried to optimize processing and reliability. Fine line structures down to 14 mum have been demonstrated. These were also found to pass reliability testing. Additionally, FE modeling was performed to understand the predicted reliability of microvias in these RXP-4 materials.
Archive | 2009
Sankar Paul; Christopher J. Caisse; Dirk M. Baars; Allen F. Horn
Archive | 2010
Sankar Paul; Scott Kennedy; Dirk M. Baars
Archive | 2011
Dirk M. Baars; Dale J. Doyle; Sankar J. Paul; Diana J. Williams; Carlos L. Barton
Archive | 2006
Robert C. Daigle; Amit Das; Sankar Paul; Dirk M. Baars; Allen F. Horn
Archive | 2011
Dirk M. Baars; Sankar Branford Paul