Do Soo Jeong

Multi-chip package

Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements

Semiconductor device package having twice-bent tie bar and small die pad

Stacked chip package device employing a plurality of lead on chip type semiconductor chips

Wire bond packages for semiconductor chips and related methods and assemblies

Chip-size package (CSP) using a multi-layer laminated lead frame

Method for manufacturing a chip scale package having copper traces selectively plated with gold

Lead frames including extended tie-bars, and semiconductor chip packages using same

Method for manufacturing a chip scale package

Semiconductor component with lead frame-mounted chip