Domingo G. Garcia

A Flexible Hardware Architecture for Wavelet Packet Transform With Arbitrary Tree Structure

We present a new hardware architecture for implementing the orthogonal wavelet packet transform with an arbitrary wavelet tree. The architecture is flexible enough to accommodate an arbitrary wavelet filter and an arbitrary tree up to a certain depth. The tree structure is specified through an efficient register parameterization architecture. We provide a detailed description of the different modules and complexity estimates for the application-specified integrated circuit implementation of the proposed architecture.

The Lab-In-A-Box project: An Arduino compatible signals and electronics teaching system

The Stanford “Lab-In-A-Box” project comprises an open source hardware and software tool chain for teaching signal processing and analog electronics. It is intended to improve the teaching of these concepts by providing a platform that is more open and understandable and by lowering the economic barriers to students interested in the field. To do this, the Lab-In-A-Box brings a full powered Digital Signal Processor (DSP) core to the popular Arduino microcontroller environment and marries it with a simple to use analog front end (AFE). The software platform provided with the Lab-In-A-Box includes an Arduino-like development environment that facilitates learning and quick development of signal processing applications without abstracting away the intricacies of a practical implementation. This system has been used to create several teaching examples and has been tested in courses at Stanford University.

Implementation of a parallel DFE using residue number system

A parallel decision feedback equalizer (DFE) implementation using residue number system (RNS) is considered When the DFE implementation for a system requires a wide input data width and high sampling rates, RNS provides a speed advantage over conventional approaches. This speed advantage can be obtained without an overall increase in hardware complexity. We present the results of our initial feasibility study implementing a DFE using RNS. A comparison of RNS and conventional approaches is given in terms of gate counts and gate delays.<<ETX>>