Dominik Lorenz

Aging analysis of circuit timing considering NBTI and HCI

We present an aging analysis flow able to calculate the degraded circuit timing. To the best of our knowledge it is the first approach on gate level so far capable of analyzing the impact of the two dominant drift-related aging effects - NBTI and HCI - on complex digital circuits. The aging-aware gate model used to compute the aged circuit timing provides not just the cell delay degradation, but also the degradation of the output slope. To get more accurate results, the individual workload of a gate can be considered.

Aging analysis at gate and macro cell level

Aging, which can be regarded as a time-dependent variability, has until recently not received much attention in the field of electronic design automation. This is changing because increasing reliability costs threaten the continued scaling of ICs. We investigate the impact of aging effects on single combinatorial gates and present methods that help to reduce the reliability costs by accurately analyzing the performance degradation of aged circuits at gate and macro cell level.

Efficiently analyzing the impact of aging effects on large integrated circuits

Abstract Time-dependent variations have not received a lot of attention in the past. However, they gain in importance with each now process generation. Our goal is an accurate analysis of the timing degradation of large integrated circuits caused by aging effects. We present an aging-analysis flow on gate level that considers the two dominant aging-effects, NBTI and HCI. Furthermore, an aging model on module-level is proposed to handle even larger circuits. This aging model is on average 30× faster than an analysis on gate level while providing the same accuracy.

Monitoring of aging in integrated circuits by identifying possible critical paths

Abstract Aging of integrated circuits can no longer be neglected in advanced process technologies. Especially the strong dependence of the delay degradation of digital circuits on the workload is still an unsolved problem. If the workload is not known exactly, only a worst-case design can guarantee that the circuit works correctly during the entire specified lifetime. We propose a method that enables a better-than-worst-case design. To assure that this design still works correctly during the specified lifetime, the circuit is monitored periodically and countermeasures are taken if the circuit degrades too much. Our main contribution is an algorithm to identify all paths that might become critical during the specified lifetime. These are called possible critical paths (PCPs). This is the first approach that also considers local process variations for finding the PCPs. Without considering process variations, it is not guaranteed that all possible critical paths are found. In addition, we could reduce the number of paths that have to be monitored by 2.7× compared to a state-of-the-art approach.

Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene).

Abstract The presented aging analysis flow is able to calculate the degraded circuit timing on gate level. It is the first approach considering the impact of the two dominant drift-related aging effects — NBTI and HCI. Our proposed aging-aware gate model, AgeGate, is very accurate. It provides the degraded output slope in addition to the degraded gate delay, and it calculates individual parameter degradations for all transistors of a logic gate. Zusammenfassung Die vorgestellte Analysemethode ist in der Lage die Degradation der Schaltungseigenschaften durch Alterung auf Gatterebene zu bestimmen. Es ist der erste Ansatz, der sowohl NBTI als auch HCI berücksichtigt — die beiden dominanten Alterungseffekte. Das vorgeschlagene Alterungsgattermodell, AgeGate, ist sehr genau, da es, zusätzlich zur degradierten Gatterlaufzeit, auch eine gealterte Ausgangsflankensteilheit liefert. Ausserdem berechnet es individuelle Parameterdriften für alle Transistoren eines Logikgatters.

Effect of voids on thermo-mechanical reliability of chip resistor solder joints: Experiment, modelling and simulation

Abstract With the introduction of lead-free solder alloys, the effect of voids on solder joint reliability has rapidly gained importance. In this study, a first analysis of X-rayed CR0805 solder joints shows a significant reduction in void content, from 20% down to 2.5%, after vacuum soldering. The statistical analysis of the void distribution demonstrates that the vacuum option reduces number of voids and median diameter of voids in comparison to the convection soldering process. A subsequent accelerated thermal cycling test of these analysed test vehicles, according to JESD22-A104D, indicates the tendency of a higher characteristic life time for higher void content. In contrast to these findings, the 1% to failure criterion reveals a higher reliability for lower voiding. During the finite element method (FEM) modelling part of this study, two modelling approaches of void implementation into solder joint geometry are investigated: modelling with a constant volume of the standoff for different void contents, and a modelling approach with a random combination of void content and volume of standoff. The modelling approach with the random combination reveals that voids can reduce the lifetime in the “worst case” parameter combination. In particular, the 1% time to failure rate indicates a quantitative correlation with the experimental results. Furthermore, the FEM results suggest a higher impact on reliability for a single void in comparison to a distribution of multiple voids with similar void content. Finally, the FEM study shows a high sensitivity of predicted life time with respect to the standoff height. Based on this finding, the CR0805 solder joint geometry is examined using optical inspection and cross-section polishes with the outcome that the better wetting behaviour during vacuum soldering causes a reduction of the solder alloy volume and consequently further decreases the standoff height.