Dominik Meyer

Wireless sensor/actuator device configuration by NFC

In the area of building automation, many sensor or actuator devices are tiny embedded systems which are installed throughout the building. The sensors gather information about the current environment (e.g., the temperature, number of people in a room, etc.) and the actuators interact with the environment (e.g., controlling lights, heating, or door access). A central unit controls these devices (wirelessly or by wire), therefore all devices need at least a unique id throughout the system, and in many cases some more configuration or authentication data. New or replaced devices have to be registered with the central unit in order to enable correct control. Thus, the person installing a new device has to prepare it in terms of at least setting an id before it can be connected to the network. This can be tedious work, especially for untrained workers. This paper proposes adding an NFC module as an enhancement for standard devices. The devices can then be configured on site using a standard smart phone running an appropriate application. This eliminates the need to pre-configure devices using a programmer tool. The presented application enables (first-time or re-) configuration of wireless embedded devices. The prototype features an ATmega 328P micro-controller from Atmel and a M24SR02-Y NFC chip from STMicroelectronics.

Multicore reconfiguration platform an alternative to RAMPSoC

The current state of the art in processor performance improvement is multicore-processor systems. These systems offer a number of homogeneous and static processor cores for the parallel distribution of computational tasks. A novel idea in this research field is introduced by the Runtime Adaptive Multi-Processor System-on- Chip (RAMPSoC) approach. It uses a dynamic and partial reconfigurable system to offer a heterogeneous multicore-processor system. It is runtime adaptable to applications needs and provides a high degree of freedom for system design and task distribution. The continuation of this idea is the Multicore Reconfiguration Platform (MRP) presented in this paper. Its fine grained reconfiguration framework offers a higher degree of freedom and achieves a better FPGA space exploitation, reduced power consumption and a more precise adaption to application requirements.

A threat-model for building and home automation

Security and privacy are very important assets within building and home automation because the System Control Unit (SCU) stores and processes a huge amount of data about the inhabitants or employees of the building. This data is necessary for managing the building and increasing the convenience of persons within. But this data can also be used to create a movement profile, monitor working times, and draw conclusions about peoples health situation. Modern smart home implementations also control many actuators within the building including doors, windows, locks, and fire extinguisher. These increase security and safety, but unauthorized control can reduce the security and can even be harmful to persons. Therefore, identifying the different security and privacy threats is very important and helps system engineers and system managers to develop and deploy secure systems. This work presents an abstract model of a building automation system and some attack trees which simplify threat identification. Attack trees are common in secure software development and secure system deployment. An example smart home deployment is evaluated using the proposed model and attack trees to show the feasibility.

Operating System Concepts for Reconfigurable Computing

One of the key future challenges for reconfigurable computing is to enable higher design productivity and a more easy way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually supported and enforced by an operating system. This article gives historical review and a summary on ideas and key concepts to include reconfigurable computing aspects in operating systems. The article also presents an overview on published and available operating systems targeting the area of reconfigurable computing. The purpose of this article is to identify and summarize common patterns among those systems that can be seen as de facto standard. Furthermore, open problems, not covered by these already available systems, are identified.

Architectural requirements for constructing hardware supported sandboxes

Malicious stealth software can detect being executed in a virtual machine and thus behave differently. If the system virtualization however is moved to the hardware level, the malware is fooled and can be identified and monitored. This paper gives an overview of requirements for a hardware supported virtualization facility implemented on an FPGA. These requirements are examined along the lines of the basic parts of a typical computer architecture: the processor, memory, and devices. A proof-of-concept demonstrator was implemented on several Xilinx Evaluation boards.

Generic operating-system support for FPGAs

Field Programmable Gate Arrays (FPGAs) are by now common in industrial applications and research. The industry utilizes FPGAs for prototyping, small scale hardware productions, and telecommunication hardware. The deployment of FPGAs in research is often High Performance Computing (HPC) centric. But FPGAs are not used in General Purpose Computing (GPC) very often because of many factors, including missing Operating System (OS) support. This paper presents the idea of integrating FPGAs in OSs for standard personal computers, such as Linux, Mac OS X and Microsoft Windows. The goal of this integration is improving the acceptance of hardware acceleration for applications within software companies through separating hardware and software completely, and an easy hard- and software Application Programming Interface (API). Another goal is to improve the acceptance of FPGAs at the end-user by reducing the connection complexity of FPGAs and standard personal computers. The user should use them just by plug and play. To achieve these goals the paper introduces OS support for identifying and configuring FPGAs without vendor specific tools, and for bidirectional communication between the host computer and components configured inside the FPGA.

Wireless sensor/actuator device configuration by NFC with secure key exchange

Modern building automation systems are networks of sensors (heat, power, light, humidity, air presure, etc.), actuators (air conditioners, door openers, window openers, lamps, switches, alarms, etc.) and control units. The network technology is typically hybrid. Cables, communication via power lines and wireless technologies are used in one logical network. Large buildings (like office or public buildings) or even plants require the installation of a large amount of such devices. All devices need to be personalized after their installation, i.e., they need a unique ID in order to be locatable and logically addressable. In security critical environments they need to obtain initial secret keys to enable secure communication methods. The initialization is usally done after the installation of the device. This can be done with special wired initialization equipment or wirelessly by radio or, as it is assumend in this paper, by Near Field Communication (NFC). As NFC itself is a publically readable protocol, it needs a secure public key exchange method to provide devices with initial keys. This paper shows how to initialize new or replaced devices using an Android app with NFC and focusses on the public key exchange mechanism by Diffie-Hellman to prepare the device for encryption.

Comparison and evaluation of cache parameters for softcores on FPGAs

Using caches is a common technique to enhance the computational performance of a processor which would otherwise be limited by the timing of a systems main memory. Softcores instantiated inside an FPGA also require caches to achieve a suitable computational performance whenever they use large amounts of memory provided by FPGA external memory resources like DDR-memory. However, the internal structures of an FPGA limit the freedom in designing caches for theses softcores. Therefore, this paper examines the impact of several cache parameters like the total cache size and the degree of associativity on the resource usage, system clock frequency and resulting computational performance of a softcore base system inside an FPGA. As a result, design guidelines/rules for parameterizing softcore-caches within an FPGA are deduced.

CloudSynth — Outsourcing hardware synthesis into the cloud

Synthesizing hardware from a Hardware Description Language (HDL) for Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) is very important today because many companies produce ASICs or use FPGAs for prototyping or High Performance Computing (HPC). Although, the synthesis, mapping and routing processes are well understood and good covered by research, some challenges in the operation of these processes exist, such as easy design space exploration, commercial license management, and different software version support which are not focus of research yet. This paper addresses these challenges by proposing the outsourcing of the whole hardware synthesis process into the cloud. A complete cloud-based synthesis service is presented consisting out of a command line client to deploy a synthesis process into the cloud, a remote web-service to schedule synthesis jobs within a cluster of servers or virtual machines, and a control webservice on each of these machines to start and stop the synthesis process. This service is evaluated against the standard local synthesis flow.

Clock speed optimization of runtime reconfigurable systems by signal latency measurement

Partial runtime reconfiguration is a feature of modern Field Programmable Gate Arrays (FPGAs). It allows the reconfiguration of some parts of the FPGA, while other parts are still running and doing computations. The design flow to create a partially run-time reconfigurable system includes the partitioning of a FPGA into multiple collaborating Reconfigurable Modules (RMs), as part of the floor-planning design stage, and the development of an interconnection network. The latency of the chosen interconnection network determines the maximum clock speed the components inside the RMs can run at. The customary way of choosing design constraints to achieve the highest possible speed can lead to very long placement and routing times or even to an un-routable design. Eventually, the the Time To Market (TTM) of a product can be inreased. This paper proposes measuring the latencies of the interconnection network after a relaxed configuration phase. This is achieved by configuring two different kinds of components into the RMs and measure the round trip time of the network between them. Thus, the best placement of reconfigurable components, as well as the maximum clock rate of a given configuration can be calculated, and set without the need to rebuild the system. This enables the developer to place components into the RMs according to their clock speed requirements, without the need to reconfigure or rebuild the full system. This paper also presents some example measurements and an example placement of a small microcontroller.