Dominique Heller

GAUT: A High-Level Synthesis Tool for DSP Applications

This chapter presents GAUT, an academic and open-source high-level synthesis tool dedicated to digital signal processing applications. Starting from an algorithmic bit-accurate specification written in C/C++, GAUT extracts the potential parallelism before processing the allocation, the scheduling and the binding tasks. Mandatory synthesis constraints are the throughput and the clock period while the memory mapping and the I/O timing diagram are optional. GAUT next generates a potentially pipelined architecture composed of a processing unit, a memory unit and a communication with a GALS/LIS interface.

OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters

Modern embedded MPSoC designs increasingly couple hardware accelerators to processing cores to trade between energy efficiency and platform specialization. To assist effective design of such systems there is the need on one hand for clear methodologies to streamline accelerator definition and instantiation, on the other for architectural templates and run-time techniques that minimize processors-to-accelerator communication costs. In this paper we present an architecture featuring tightly-coupled processors and accelerators, with zero-copy communication. Efficient programming is supported by an extended OpenMP programming model, where custom directives allow to specialize code regions for execution on parallel cores, accelerators, or a mix of the two. Our integrated approach enables fast yet accurate exploration of accelerator-based HW and SW architectures.

Multiple Word-Length High-Level Synthesis

Digital signal processing (DSP) applications are nowadays widely used and their complexity is ever growing. The design of dedicated hardware accelerators is thus still needed in system-on-chip and embedded systems. Realistic hardware implementation requires first to convert the floating-point data of the initial specification into arbitrary length data (finite-precision) while keeping an acceptable computation accuracy. Next, an optimized hardware architecture has to be designed. Considering uniform bit-width specification allows to use traditional automated design flow. However, it leads to oversized design. On the other hand, considering non uniform bit-width specification allows to get a smaller circuit but requires complex design tasks. In this paper, we propose an approach that inputs a C/C++ specification. The design flow, based on high-level synthesis (HLS) techniques, automatically generates a potentially pipeline RTL architecture described in VHDL. Both bitaccurate integer and fixed-point data types can be used in the input specification. The generated architecture uses components (operator, register, etc.) that have different widths. The design constraints are the clock period and the throughput of the application. The proposed approach considers data word-length information in all the synthesis steps by using dedicated algorithms. We show in this paper the effectiveness of the proposed approach through several design experiments in the DSP domain.

Uninterpreted co-simulation for performance evaluation of Hw/Sw systems

Performance modeling and evaluation of embedded hardware/software systems is important to help the CoDesign process. The hardware/software partitioning needs to be evaluated before synthesizing the solution. This paper presents a co-simulation technique based on the use of an uninterpreted model able to accurately represent the behavior of the whole system. The performance model includes two complementary viewpoints: the structural viewpoint which describes the functional structure, the hardware structure, the functional to hardware mapping, and the behavioral viewpoint which specifies the temporal evolution of each function or process. Attributes are added to the graphical model to specify the local properties of all components. The performance properties of the solution are obtained by simulation with VHDL. Software functions are executed according to the availability of an execution resource which simulates a microprocessor. This technique leads to rapidly obtain a lot of results by modifying appropriate parameters of the model, and so to easily scan the CoDesign space to decide on the best implementation. This modeling and estimation technique is fully integrated in a whole development process based on the MCSE methodology.

Functional-level synthesis with VHDL

The authors describe a procedure and a tool for ASIC synthesis with VHDL. They show that the functional level which they define and use as the design input provides a synthesis level located between the system-level synthesis and the RT-level synthesis. The described design and synthesis process is based on a complete methodology and the use of its functional model allows designers to describe their solutions according to two views: an organizational view which defines the internal structure, and a behavioral view which describes the activity of each function. Tools, mainly graphical, have been developed as an aid to capture the design description. After that, a generator is used to obtain the complete VHDL model at a RT-level model which is simulatable and synthesizable. Such a tool leads to obtaining of ASIC prototypes efficiently and in an incremental manner. Results for some ASICs designed by the authors are given to illustrate the benefit of the proposed method and the significance of the functional level.<<ETX>>

Bitwidth-aware high-level synthesis for designing low-power DSP applications

Digital Signal Processing (DSP) applications are widely used from wireless communications to automotive. Their ever growing complexity and throughput still require significant parts to be implemented as dedicated hardware accelerators. A High-Level Synthesis (HLS) flow to automatically generate hardware accelerators for DSP applications is proposed in this paper. By considering bit-width information during all the synthesis process both area and power consumption are optimized. Experimental results show that the proposed approach allows to generate architectures that offer better computation accuracy for a given area and/or power consumption. Effectiveness of the approach is shown through several design experiments in the DSP domain realized on a Xilinx Virtex-5 FPGA.

A programmable multi-language generator for CoDesign

This paper presents an innovative technique to efficiently develop hardware and software code generators. The specification model is first converted into its equivalent data structure. Target programs result from a set of transformation rules applied to the data structure. These rules are written in a textual form named Script. Moreover, transformations for a specific code generator are easier to describe because our solution uses a template of the required output as another input. The result is a meta-generator entirely written in Java. The concept and its implementation have been demonstrated by developing a C/WxWorks code generator, a behavioral VHDL generator, a synthesizable VHDL generator.

Fast template-based heterogeneous MPSoC synthesis on FPGA

Our contribution lies in offering a fast and parametrized domain-space exploration to the designer, whose expertise drives the whole process while staying the actor of added-value creation. In this paper, we present two new features and two important improvements of our H-MPSoC synthesis framework. The first one is a new template-based approach for automated design space exploration and synthesis. A template describes an architecture model for a specific domain and has three levels of specifications each representing a different level of design expertise. We also rely on the Model-Driven Architecture (MDA) paradigm to provide flexibility, reusability and code generation for different FPGA targets. We have refined the communication models to get more accurate performance estimations. Finally, we also improved our mapping decision algorithm that drastically reduces the simulation time. The output is the synthesizable code of the hardware architecture, the adapted C code of the application and the project files for FPGA design tools. We use an MJPEG decoder as a case-study to validate our framework on a Xilinx FPGA.

A framework for high-level synthesis of heterogeneous MP-SoC

In this paper we propose an ESL synthesis framework which, from the C code of an application and a description of a generic architecture, automatically explores and generates a complete synthesizable version of a H-MPSoC architecture along with the adapted code application. We developed a Design Space Exploration (DSE) algorithm that merges hardware specialization, data-parallelism exploration, processor instantiation and task mapping according to user performance and cost constraints. We also inserted HLS in the DSE loop and get fast exploration of hardware acceleration. A new ESL framework is presented, it combines our contributions with some legacy tools issued from our and another team. We validated our framework with a case study of an MJPEG decoder.

An interactive modeling and generation tool for the design of Hw/Sw systems

This paper addresses the design of nowadays embedded hardware and software systems. We propose an interactive tool enabling designers: to easily describe and configure system solutions at the functional and the architectural levels, to interactively define properties for all internal components, to incrementally generate executable code programs for both hardware and software components. The basis of our approach is the MCSE methodology which specifies the description model and the method designers can follow to develop Hw/Sw solutions. The graphical model useful for system-level description includes the functional structure, behaviors of components, the physical architecture, the functional/spl rarr/architecture mapping after Hw/Sw partitioning. Our model also includes the concept of attribute to specify standard and user-defined properties for all components. These attributes are interactively edited and they directly drive a set of code generators, each one focussing a specific target (C with WxWorks, synthesizable VHDL, Hw/Sw interface, C++).