Dominique Thiebaut

Footprints in the cache

This paper develops an analytical model for cache-reload transients and compares the model to observations based on several address traces. The cache-reload transient is the set of cache misses that occur when a process is reinitiated after being suspended temporarily. For example, an interrupt program that runs periodically experiences a reload transient at each initiation. The reload transient depends on the cache size and on the sizes of the footprints in the cache of the competing programs, where a program footprint is defined to be the set of lines in the cache in active use by the program. The model shows that the size of the transient is related to the normal distribution function. A simulation based on program-address traces shows excellent agreement between the model and the observations.

Improving disk cache hit-ratios through cache partitioning

An adaptive algorithm for managing fully associative cache memories shared by several identifiable processes is presented. The on-line algorithm extends an earlier model due to H.S. Stone et al. (1989) and partitions the cache storage in disjoint blocks whose sizes are determined by the locality of the processes accessing the cache. Simulation results of traces for 32-MB disk caches show a relative improvement in the overall and read hit-ratios in the range of 1% to 2% over those generated by a conventional least recently used replacement algorithm. The analysis of a queuing network model shows that such an increase in hit-ratio in a system with a heavy throughput of I/O requests can provide a significant decrease in disk response time. >

On the fractal dimension of computer programs and its application to the prediction of the cache miss ratio

Fractal geometry is proposed as a powerful measure of program behavior, and its application to the prediction of the miss ratio of programs in fully associative caches is presented. Programs are modeled as one-dimensional fractal random-walks. The fractal cache model is based on the parameterization of a program trace by a small number of constants, one of which is the fractal dimension of the program. The model is validated by trace-driven simulations of several program traces. With this model, it is possible to read the trace of a program once, and then predict the behavior of the miss ratio curve of that program in fully associative caches of varying sizes. >

Synthetic traces for trace-driven simulation of cache memories

Two techniques for producing synthetic address traces that produce good emulations of the locality of reference of real programs are presented. The first algorithm generates synthetic addresses by simulating a random walk in an infinite address-space with references governed by a hyperbolic probability law. The second algorithm is a refinement of the first in which the address space has a given finite size. The basic model for the random walk has two parameters that correspond to the working set size and the locality of reference. By comparing synthetic traces with real traces of identical locality parameters, it is demonstrated that synthetic traces exhibit miss ratios and lifetime functions that compare well with those of the real traces they mimic, both in fully associative and in set-associative memories. >

A model of workloads and its use in miss-rate prediction for fully associative caches

A mathematical model for the behavior of programs or workloads is presented and from it is extracted the miss ratio of a finite, fully associative cache (or other first-level memory) using least-recently-used replacement under those workloads. To obtain miss ratios, the function u(t, L), defined to be the number of unique lines of size L referenced before time t, is modeled. Empirical observations show that this function appears to have the form u(t, L)=(W L/sup a/t/sup b/) (d/sup log/ /sup L log t/) where W, a, b, d are constants that are related, respectively, to the working set size, locality of references to nearby addresses (spatial locality), temporal locality (locality in time not attributable to spatial locality), and interactions between spatial locality and temporal locality. The miss ratio of a finite fully associative cache can be approximated as the time derivative of u(t, L) evaluated where the function has a value equal to the size of the cache. When the miss ratios from this model are compared to measured miss ratios for a representative trace, the accuracy is high for large caches. For smaller caches, the model is close but not highly precise. >

Modeling live and dead lines in cache memory systems

An analytical model that predicts the fraction of live and dead lines present in a cache memory in a multitasking environment is presented. The model is two-fold. The first portion evaluates the number of live lines created in a fully associative cache during the execution of a process. The second portion models the interaction of two processes that share a cache and run in an interleaved fashion. The model admits direct-mapped, set-associative, and fully associative cache architectures. The complete model assumes a hyperbolic (or fractal) model of program behavior. It predicts the variations of the total number of lines (footprint) as well as the number of live lines held by a process in the various caches as a function of the number of cache accesses. The accuracy of the model is validated through trace driven simulations. >

Two economical directory schemes for large-scale cache coherent multiprocessors

Cache coherence problem is a major issue in the design of shared-memory multiprocessors. As the number of processors grows, traditional bus-based snoopy schemes for cache coherence are no longer adequate. Instead, the directory-based scheme is a promising alternative for the large-scale cache coherence problem. However, the storage overhead of (full-map) directory scheme may become too prohibitive as the system size goes up. This paper presents two distributed directory schemes, the tree directory and the hierarchical full-map directory, to deal with the storage overhead problem. Preliminary trace-driven evaluations show that the performance of our schemes compares favorably to the full-map directory scheme, while reducing the storage overhead by over 90%. These two schemes should lend themselves to the design and implementation of large-scale cache coherent multiprocessors.

Not multi-, but many-core: designing integral parallel architectures for embedded computation

Recent embedded systems have switched to fully programmable parallel architectures. To make sure all corner cases usually present in real applications are supported and efficiently implemented in this switch of implementation, new solutions must be found. We introduce the integral parallel architecture (IPA) as a solution supporting intensive data computation in System-on-a-chip (Soc) implementations, fitting in a small area, and requiring low power. An IPA supports naturally all three possible styles of parallelism: data, time, and speculative. As an illustrative example, we present the BA1024 chip, a fully programmable SoC designed by BrightScale, Inc. for HDTV codecs. Its main performance figures include 60 GOPS/Watt and 2 GOPS/mm2, representing an efficient IPA approach for embedded computation.

From the fractal dimension of the intermiss gaps to the cache-miss ratio

This work extends a model proposed by Voldman, Mandelbrot, et al. on the fractal nature of the gaps separating cache misses, and shows how the fractal dimension of the gap distribution can be used to predict the miss ratio experienced by the program that has generated the series of cache misses. This result supports the thesis that the fractal dimension of the distribution of the intermiss gaps is a potentially powerful measure for program characterization.

A hierarchical directory scheme for large-scale cache-coherent multiprocessors

Cache coherence problem is a major design issue for shared-memory multiprocessors. As the system size scales, traditional bus-based snoopy cache coherence schemes are no longer adequate. Instead, the directory-based scheme is a promising approach to deal with the large-scale cache coherence problem. However, the storage overhead of directory schemes often becomes too prohibitive as the system size increases. The paper proposes the hierarchical full-map directory to reduce the storage requirement while still achieving satisfactory performance. The key point is to exploit the inherent geographical interprocessor locality among shared data in the parallel programs. Trace-driven evaluations show that the performance of the proposed scheme compares competitively to the full-map directory scheme, while reducing the storage overhead by over 90%. The proposed hierarchical full-map directory scheme seems to be a promising hardware approach for handling cache coherence in the design of future large-scale multiprocessor memory systems.<<ETX>>