Donald F. Wann

An On-Line Digital-Computer System for the Semiautomatic Analysis of Golgi-Impregnated Neurons

Rapid and accurate measurements of neuronal processes in Golgi preparations are possible with the aid of a small computer (Glaser and Van der Loos, 1965). This paper describes a system for doing this, using a small digital computer which controls stepping motors (0.5-?m steps) attached to the stage (x, y axes) and fine focus (z axis) of a microscope. The observer tracks the processes, topological information, such as the location of the soma, dendritic origins, branch points, and ends of processes, is signaled to the computer by special controls, and the x, y, and z coordinates of each are stored in digital format. The computer printout yields 1) individual x, y, and z coordinates with associated topological identifiers; 2) quantitative data for each dendritic segment in order (i.e., primary and secondary branches, etc.); and 3) computes the actual linear dimensions of each segment in microns. An associated oscilloscope display can 1) display the whole neuron, or individual processes, by connecting recorded points by vectors; 2) identify each dendrite; 3) rotate (continuously or by a specified angle) the whole cell, or individual dendrites, around any selected point or axis; and 4) indicate spatial relationships by dynamic rotation, intensity modulation, or stereo pairs. The performance of this system has been evaluated for accuracy and the repeatability of measurements.

Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region

The interaction problem between asynchronous logic elements is formulated with emphasis on the synchronizer. A detailed analytic treatment of the binary flip-flop action in the metastable region is presented. The principle result is to predict, in a probabilistic manner, the time necessary to move from the metastable point to one of the stable boundaries. The effects of circuit time constant and circuit noise are discussed in detail. Theoretical results are correlated with laboratory measurements and suggestions for acceptable probability of error performance are given.

Conjoined computer systems: an architecture for laboratory data processing and instrument control

A new computer system organization and implementation is described and its application to problems in both clinical and research laboratory biomedical applications is outlined. This system, called a Conjoined Computer System to emphasize the idea of computer coordination, consists of a few storedprogram computers, each with a fixed assigned task, and inter-connected with combined data and control paths which may be easily changed. Such systems appear to be useful in situations where a) one or more major laboratory peripheral devices are included, b) operational speed is required which is greater than that which can be obtained from a single processor implementation, and c) the algorithms utilized can be partitioned into two or more machines such that only moderate intercomputer communication rates are needed. This architecture offers the possibility of simplifying the peripheral interfacing, reducing total computation time, allowing rapid system reconfiguration, enforcing the discipline required for structured programming, and, by means of a centralized program development console, increasing the efficiency of program development.

VLSI Based Interconnection Networks

Interest in tightly coupled multiprocessor computer systems has grown as the possibilities for high performance with such systems have been recognized. Central to their design is the structure of the network over which the processors communicate. Unless properly designed, such networks can be both a cost and performance bottleneck. This paper focuses on the design of VLSI communications networks, this is, on communications network which can be placed on a single VLSI chip. Traditional SSI-based boost and complexity measures for such networks have principally involved switch aggregate counts. In a VLSI domain, however, more appropriate measures involve chip area,... Read complete abstract on page 2.

Threshold Logic Design of Pulse-Type Sequential Networks

A modification of the conventional design method for pulse-type sequential logic is developed in which threshold gates are used in all of the combinational portions of the circuit. The canonical configuration, memory element employed, tabular design aids, etc., found in the conventional method were changed as necessary in order to use more effectively the unique properties possessed by threshold elements. A theorem providing insight for threshold gate realization is given and a classification of sequential functions is discussed in order to facilitate the understanding and use of the new process. Finally, examples are presented showing a significant advantage of the present method in both gate and transistor economy over conventional design.

Teaching computer design using macromodules

This paper describes the teaching of computer design using a new and quite unusual hardware aid, macromodules. Of all the new areas emerging in Computer Science the teaching of computer structures, from an engineering viewpoint, has continually challenged the professional educator. This has in a sense presented a dilemma to him: for digital computer system design requires a broad look at a variety of configurations, but also seems to require a comprehensive examination of individual circuit details in order to remain in a practical atmosphere. As is well known, such detailed investigation of many systems is virtually impossible in the time allotted in most cirricula. Introduction of the macromodular concept, however, has permitted individual students, in one or two semesters, to achieve realizabledesigns of such devices as I/O channels, microprogrammed machines, complete small digital computers, floating point arithmetic systems and list processing hardware.

Regular Array Processors: Asynchronous Versus Clocked Control

Parallel computing structures consisting of large numbers of processors require synchronization so that data communication among processors is possible. Two basic methods of data synchronization, synchronous and asynchronous, are considered. The synchronous or clocked method uses a global clock for synchronization. Clock skew and clock line charge and discharge times both increase with system size. This decreases the data rates achievable and prevents the design of highly modular systems. The asynchronous method has no global control structure and results in a modular and expandable system with the data rate being independent of system size. It is however pin intensive.... Read complete abstract on page 2.