Donald T. Tang

A conference key distribution system

Encryption is used in a communication system to safeguard information in the transmitted messages from anyone other than the intended receiver(s). To perform the encryption and decryption the transmitter and receiver(s) ought to have matching encryption and decryption keys. A clever way to generate these keys is to use the public key distribution system invented by Diffie and Hellman. That system, however, admits only one pair of communication stations to share a particular pair of encryption and decryption keys, The public key distribution system is generalized to a conference key distribution system (CKDS) which admits any group of stations to share the same encryption and decryption keys. The analysis reveals two important aspects of any conference key distribution system. One is the multitap resistance, which is a measure of the information security in the communication system. The other is the separation of the problem into two parts: the choice of a suitable symmetric function of the private keys and the choice of a suitable one-way mapping thereof. We have also shown how to use CKDS in connection with public key ciphers and an authorization scheme.

Block codes for a class of constrained noiseless channels

A class of discrete noiseless channels having upper and lower bounds on the separation between adjacent nonzero input symbols is considered. Recursion relations are derived for determining the number of input sequences which satisfy the constraints for all block lengths, and the asymptotic information rate is calculated. Applications to compaction and synchronization are discussed. An optimal algebraic block coding scheme for such channels is developed.

Iterative exhaustive pattern generation for logic testing

Exhaustive pattern logic testing schemes provide all possible input patterns with respect to an output in the set of test patterns. This paper is concerned with the problem that arises when this is to be done simultaneously with respect to a number of outputs, using a single test set. More specifically, in this paper we describe an iterative procedure for generating a test set consisting of n- dimensional vectors which exhaustively covers all k-subspaces simultaneously, i.e., the projections of n-dimensional vectors in the test set onto any input subset of a specified size k contain all possible patterns of k-tuples. For any given k, we first find an appropriate N (N > k) and generate an efficient N-dimensional test set for exhaustive coverage of all k-subspaces. We next develop a constructive procedure to expand the corresponding test matrix (formed by taking test vectors as its rows) such that a test set of N2-dimensional vectors exhaustively covering the same k-subspaces is obtained. This procedure may be repeated to cover arbitrarily large n (n = N2i after i iterations), while keeping the same k. It is shown that the size of the test set obtained this way grows in size which becomes proportional to (log n) raised to the power of [log (q + 1)], where q is a function of k only, and is approximated (bounded closely below) by k2/4 in binary cases. This approach applies to nonbinary cases as well except that the value of q in an r-ary case is approximated by a number lying between k2/4 and k2/2.

A general packing algorithm for multidimensional resource requirements

Many problems in resource allocations, memory allocation, and distributed computer system design can be formulated as problems of packing variablesized items into fixed-sized containers in order to minimize the total number of containers used. In this paper, a generalized packing algorithm that encompasses many well-known heuristic packing algorithms is proposed. Simulation results on this generalized packing algorithm are described, and their implications are discussed. The objective of this paper is to investigate the performance of various heuristic packing algorithms within a general framework, to obtain numerical estimates on their efficiency, and to provide guidelines on the use of these algorithms.

A Hierarchical Global Wiring Algorithm for Custom Chip Design

We present a global wiring algorithm used in a top-down physical design environment, i.e., macros are laid out after global wiring is done, and wires are allowed to pass through macros (the wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained through a series of refinement as the problem is recursively decomposed into a set of small-sized problems and then solved efficiently. The worst-case run-time for an arbitrary slicing tree (totally skewed) is O(M /sup 2/ N). When the floorplan is represented by a balanced slicing tree, the run-time of the overall algorithm is O(MN), where M is the number of macros and N the number of nets. The algorithm has been implemented in the C language and is used for chip designs. Experiments on both real and randomly generated designs show that the hierarchical router performs equally well as a flat global router in terms of wire length and wireability handling, but much faster in run-time (at least 10 times for an example with 100 macros and 1000 nets, and the gap being even larger for bigger-size problems).

An Algorithm for Incremental Timing Analysis

In recent years, many new algorithms have been proposed for performing a complete timing analysis of sequential logic circuits. In this paper, we present an incremental timing analysis algorithm. When an incremental design change is made on the logic network, this algorithm will identify the portion of design for which the timing is affected, and quickly derive the new arrival times and slacks. A fast incremental timing analysis is desirable for users doing interactive logic design. It is particularly important for a logic synthesis program, which needs to evaluate the circuit delays under many logic modifications.

VLSI Layout Compaction with Grid and Mixed Constraints

We investigate the modeling and solution techniques of VLSI layout compaction using the constraint graph approach under various practical design considerations. In particular, we extend the graph method to the compaction of VLSI layout with mixed grid constraints in addition to the usual minimum- and maximum-type constraints. This is a mixed integer problem. We show that it can be solved by the search of effectively longest paths, and a fast algorithm is presented

Simulating Pass Transistor Circuits Using Logic Simulation Machines

An algorithm for pass transistor simulation using the Yorktown Simulation Engine (YSE) is outlined. Implementing this algorithm yields an efficient tool for custom VLSI circuit design verification and fault simulation. Modeling of circuits under this environment is defined, including the analysis of the algorithms performance for some general circuit types. A number of specific examples are discussed in detail.

Distance-2 Cyclic Chaining of Constant-Weight Codes

The cyclic distance-2 chaining of constant-weight codes has applications in A/ D conversions as well as in combinatorial problems involving the exhaustion of m-out-of-n combinations. It is shown in this paper that such a chaining can be obtained from the Gray code circuit and its transformations. Algorithms based on several theorems derived have been developed and programmed in APL.

HIMALAYAS-A hierarchical compaction system with a minimized constraint set

A hierarchical compactor, HIMALAYAS (HIerarchical MAcro LAYout ASsembler), developed for constructing big macro layouts, is discussed. The hierarchical compaction problem is formulated as an integer linear programming (ILP) problem. Two algorithms are presented to reduce the problem size, in order to make the ILP approach practical. The first algorithm reduces the number of variables to a small set of pitch variables, while the second algorithm reduces the number of equations by restricting the constraint generation within a small set of regions, called the minimum cover. These reductions bring in considerable saving in computation time for layouts with cell repetitions or cell alignments. As a result, the ILP method can be used to solve the compaction problem for very big macros. Experimental results for MCNC benchmark examples are also given.<<ETX>>