Dong Gun Kam

A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications

A fully-integrated 16-element 60-GHz phased-array receiver is implemented in IBM 0.12-μm SiGe BiCMOS technology. The receiver employs RF-path phase-shifting and is designed for multi-Gb/s non-line of sight links in the 60-GHz ISM band (IEEE 802.15.3c and 802.11ad). Each RF front-end includes variable-gain LNAs and phase shifters with each front-end capable of 360° variable phase shift (11.25° phase resolution) from 57 GHz to 66 GHz with coarse/fine gain steps. A detailed analysis of the noise trade-offs in the receiver array design is presented to motivate architectural choices. The hybrid active and passive signal-combining network in the receiver uses a differential cross-coupled Gysel power combiner that reduces combiner loss and area. Each array front-end has 6.8-dB noise figure (at 22°C ) and the array has -10 dB to 58 dB programmable gain from single-input to output. Sixteen 60-GHz aperture-coupled patch-antennas and the RX IC are packaged together in multi-layer organic and LTCC packages. The packaged RX IC is capable of operating in all four IEEE 802.15.3c channels (58.32 to 64.8 GHz). Beam-forming and beam-steering measurements show good performance with 50-ns beam switching time. 5.3-Gb/s OFDM 16-QAM and 4.5 Gb/s SC 16-QAM links are demonstrated using the packaged RX ICs. Both line-of-sight links (~7.8 m spacing) and non-line-of-sight links using reflections (~9 m total path length) have been demonstrated with better than -18 dB EVM. The 16-element receiver consumes 1.8 W and occupies 37.7 mm2 of die area.

Modeling and measurement of simultaneous switching noise coupling through signal via transition

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach

Is 25 Gb/s On-Board Signaling Viable?

What package improvements are required for dense, high-aggregate bandwidth buses running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Hardware-validated models of advanced organic modules and printed circuit boards were used to explore these limits. Simulations of link performance performed with an internal link modeling tool allowed us to explore the effect of equalization and modulation formats at different data rates on link bit error rate and eye opening. Our link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signaling limits were then determined by extrapolating these hardware-correlated models to higher speeds, and these limits were compared to the results of recent work on on-board optical interconnects.

LTCC Packages With Embedded Phased-Array Antennas for 60 GHz Communications

A low-cost, fully-integrated antenna-in-package solution for 60 GHz phased-array systems is demonstrated. Sixteen patch antennas are integrated into a 28 mm × 28 mm ball grid array together with a flip-chip attached transmitter or receiver IC. The packages have been implemented using low temperature co-fired ceramic technology. 60 GHz interconnects, including flip-chip transitions and via structures, are optimized using full-wave simulation. Anechoic chamber measurement has shown ~ 5 dBi unit antenna gain across all four IEEE 802.15.3c channels, achieving excellent model-to-hardware correlation. The packaged transmitter and receiver ICs, mounted on evaluation boards, have demonstrated beam-steered, non-line-of-sight links with data rates up to 5.3 Gb/s.

Organic Packages With Embedded Phased-Array Antennas for 60-GHz Wireless Chipsets

A multilayer organic package with embedded 60-GHz antennas and fully integrated with a 60-GHz phased-array transmitter or receiver chip is demonstrated. The package includes sixteen phased-array antennas, an open cavity for housing the flip-chip attached RF chip, and interconnects operating at DC-66 GHz. The 28 mm 28 mm ball grid array package is manufactured using printed circuit board processes and uses a combination of liquid-crystal polymer and glass-reinforced laminates, allowing excellent 60-GHz interconnect and antenna performance. The measured return loss and gain of each antenna from 56 to 66 GHz are and , respectively. Finally, the packaged transmitter and receiver chipsets, each working with a heat sink, have demonstrated beam-steered, non-line-of-sight links with data rates up to 5.3 Gb/s using 16-quadrature amplitude modulation single-carrier and orthogonal frequency division multiplexing schemes.

A 16-element phased-array receiver IC for 60-GHz communications in SiGe BiCMOS

A 0.12-µm SiGe phased-array Rx IC for beam-steered wireless communication in the 60-GHz band is described. It has 16 RF phase-shifting front-ends with 11° digital phase resolution and hybrid passive-active RF signal combining. It achieves 7.4–7.9 dB NF (not including 12-dB array gain) over the 4 IEEE channels. The IC has a double-conversion superheterodyne Rx core with a maximum of 72 dB of power gain in 1-dB steps, and the on-chip synthesizer achieves ≪ −90 dBc/Hz Rx phase noise at 1MHz offset. The IC draws 1.8 W at 2.7 V with a die area of 38 mm2. It has been packaged with 16 antennas in a 288-pin organic BGA and phased-array beamsteering has been demonstrated, along with 5+ Gb/s wireless links using 16-QAM OFDM.

Spread spectrum clock Generator with delay cell array to reduce electromagnetic interference

In high-speed digital systems, most of the electromagnetic interference (EMI) from the system is caused by high-speed digital clock drivers and synchronized circuits. To reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional SSC generator (SSCG) has been implemented with a phase locked loop (PLL) by controlling a period jitter. However, the conventional SSCG with PLL becomes more difficult to implement at higher clock frequencies, in the gigahertz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome the problems associated with the random period jitter, we propose an SSCG with a delay cell array (DCA), which controls the position of clock transitions with a triangular modulation profile. Measurement and simulation have demonstrated that the proposed SSCG with DCA is easier to implement and more effective in attenuating the EMI compared with the conventional SSCG with PLL. The proposed SSCG with DCA was implemented on a chip using a 0.35-/spl mu/m CMOS process and achieved a 9-dB attenuation of the EMI at 390 MHz.

Circuital Modeling and Measurement of Shielding Effectiveness Against Oblique Incident Plane Wave on Apertures in Multiple Sides of Rectangular Enclosure

A simple circuital approach to evaluate the shielding effectiveness (SE) of rectangular enclosures with apertures is proposed, considering oblique incidence and polarization. The scope of the proposed model is extended beyond 1 GHz, including higher order modes of the cavity. Furthermore, apertures are not required to be on the front face of the enclosure. In the proposed model, the SE of the enclosure with apertures on multiple sides can be simply calculated by vector decomposition. The proposed model has been successfully verified by using a conventional full-wave simulation tool. We also measured the SE of a manufactured aluminum enclosure with apertures on multiple sides.

Single-element and phased-array transceiver chipsets for 60-ghz Gb/s communications

This article summarizes the development of mature and highly integrated SiGe BiCMOS ICs for gigabit-per-second communications according to the requirements of the IEEE 802.15.3c and 802.11.ad-draft standards. A single-element transceiver chipset for point-to-point communications is described with emphasis on a feature-rich yet compact 60-GHz receiver. Next, a 16-element phased-array transceiver chipset for non-line-of-sight communications is described, with emphasis on a new power-efficient phased-array transmitter. Examples of gigabit-per-second line-of-sight and non-line-of-sight link experiments are provided, and system-level implementation trade-offs are discussed.

40-Gb/s Package Design Using Wire-Bonded Plastic Ball Grid Array

A 40-Gb/s packaging solution that uses low-cost wire-bonded plastic ball grid array (WB-PBGA) technology is presented. Since such a high speed was beyond the reach of conventional package designs, a new design methodology was proposed-discontinuity cancellation in both signal-current and return-current paths. The 3-D structures of bonding wires, vias, solder ball pads, and power distribution networks were optimized for the discontinuity cancellation. Two versions of four-layer WB-PBGA packages were designed; one according to the proposed methodology and the other conventionally. The proposed design methodology was verified with full-wave simulation, passive bandwidth measurement, time domain reflectometry (TDR), eye diagram measurement, and jitter analysis.