Dong Kyue Kim

Improving Lookup Time Complexity of Compressed Suffix Arrays using Multi-ary Wavelet Tree

In a given text T of size n, we need to search for the information that we are interested. In order to support fast searching, an index must be constructed by preprocessing the text. Suffix array is a kind of index data structure. The compressed suffix array (CSA) is one of the compressed indices based on the regularity of the suffix array, and can be compressed to the k th order empirical entropy. In this paper we improve the lookup time complexity of the compressed suffix array by using the multi-ary wavelet tree at the cost of more space. In our implementation, the lookup time complexity of the compressed suffix array is O(log e/(1-e) σ n log r σ), and the space of the compressed suffix array is e?¹ nH k (T) + O(n log log n/log e σ n) bits, where σ is the size of alphabet, Hk is the kth order empirical entropy, r is the branching factor of the multi-ary wavelet tree such that 2 ≤ r ≤ √n and r ≤ O(log 1-e σ n), and 0 ＜ e ＜ 1/2 is a constant.

Secure bimodal PIN-entry method using audio signals

A Personal Identification Number (PIN) is a multiple-digit sequence widely used for user authentication. It is desirable for a PIN-entry method to be secure against two main security threats, random guessing attacks and recording attacks. Although there have been many proposals for challenge-response-based PIN-entry methods, it is well known that the only way to prevent both attacks is to physically prevent attackers from observing the challenge-response pairs, which motivates the development of PIN-entry methods that use secure secondary channels such as audio signals. To provide a guideline for designing an audio-based PIN-entry method, we propose a simple framework to transform a non-audio-based method into an audio-based one. We also present a new PIN-entry method that improves the performance of this simple transformation. Most audio-based methods in the literature are unimodal methods, that is, they transmit almost all required information through an audio channel because it was believed that this approach maximized the users performance. In this paper, however, we show that a carefully designed bimodal system may be more usable than a unimodal one. We present a new PIN-entry method whose audio channel only transmits the minimal required data while most of the challenge information is transmitted through the efficient visual channel. Our user study shows that the PIN-entry time of the proposed method is shorter than those of the previous audio-based methods, while its error rate is kept as low as that of the previous methods.

Optimization of a grounded electrode shape in gas insulated switchgear with a reversely elliptical permittivity graded insulator

An application of a functionally graded material (FGM) to the solid spacer in gas insulated switchgears (GISs) can reduce the electric field concentration at the specific region, for example, the anode or the interface between the spacer and the gas. However, the electric field stress near the triple junction of the grounded electrode with a rounded shape, which remarkably affects the insulation capability of the GIS, inversely related. Therefore, in order to prevent this, it is necessary to modify the grounded electrode geometry in the common Cubicle-GIS and apply the elliptical FGM spacer with a reverse-direction variation unlike the permittivity variations of the existing unidirectional or bidirectional distributions. In this paper, we found the proper distribution of dielectric permittivity, dug a groove in the grounded electrode near the triple junction, and performed the optimization of this grounded electrode configuration by using the design of experiments (DOE). Consequently, the electric field stress in the triple junction of the grounded electrode can be effectively reduced by using the optimally designed grounded electrode shape applying the FGM spacer.

An Efficient Architecture for a TCP Offload Engine Based on Hardware/Software Co-design *

To achieve both the flexibility of software and the performance of hardware, we design a hybrid architecture for a TCP offload engine that is based on hardware/software co-design. In this architecture, the transmission and reception paths of TCP/IP are completely separated with the aid of two general embedded processors to process data transmission and reception simultaneously. We implement this architecture based on an FPGA that has two general embedded processor cores. In the experiments based on the gigabit Ethernet, the hybrid TOE has a minimum latency of 13.5 μs. The CPU utilization is less than 3%, which is at least eighteen times lower than that of the general gigabit Ethernet adapters. The maximum unidirectional bandwidth of the hybrid TOE is 110 MB/s -comparable to that of the general gigabit Ethernet adapters-although the embedded processors operate with a clock speed that is seven times lower than that of the host CPU. By using two embedded processors, the bidirectional bandwidth of the hybrid TOE improves to about 201 MB/s, comparable to that of the general gigabit Ethernet adapters, and a 34% improvement over an experimental TOE implementation in which only one embedded processor is used.

Efficient implementation of pseudorandom functions for electronic seal protection protocols

One of the most promising applications of active RFID tags is electronic seal, which is an electronic device to guarantee the authenticity and integrity of freight containers and also provides physical protection like a lock. There are already many commercial electronic seal products and ongoing standardization activities such as ISO-18185 drafts. While electronic seals can provide freight containers with a high level of tamper resistance, the security problem of electronic seal itself should be solved, and a feasible solution would be to use symmetric key cryptography based primitives such as block ciphers and message authentication codes (MACs). This kind of approach has already been used in many security-related standards and it requires the implementation of pseudorandom functions (PRFs) for key derivation and authentication. In this paper, we consider secure and efficient implementation of PRFs on electronic seals and interrogators. We implement block cipher based PRFs and hash based PRFs and compare them from the viewpoint of efficiency. Since practical PRFs can be directly implemented using MACs, we consider implementation of various message authentication schemes; HMAC-MD5, HMAC-SHA1, AES-CBC-MAC, AES-CMAC and AESXCBC-MAC. For interrogators, we design FPGA modules for these MAC algorithms since an interrogator has to guarantee high throughput to communicate with many electronic seals simultaneously. According to our analysis, AES based MACs consume smaller areas and their throughputs are significantly higher than hash based ones. For electronic seals, we implement MAC algorithms as a form of software module (C and assembly codes) over a small-scale microcontroller. Our experimental results show that AES based modules show much better performance, which coincide with the results in hardware implementation. Finally, we improve the above implementations further, where we concentrate on the optimization of AES based MACs. We use several well-known techniques such as use of block RAMs in FPGA, and loop unrolling and register reallocation in assembly code.

Design of security enhanced TPM chip against invasive physical attacks

A TPM (Trusted Platform Module) is a hardware-based secure device that is very strong against software-based attacks; however, the keys inside a TPM can be extracted by invasive physical attacks such as memory attacks and bus probing attacks. To protect the keys from these threats, we propose a new TPM architecture based on a Physical Unclonable Function.

Finding the longest common nonsuperstring in linear time

String inclusion and non-inclusion problems have been vigorously studied in such diverse fields as molecular biology, data compression, and computer security. Among the well-known string inclusion or non-inclusion notions, we are interested in the longest common nonsuperstring. Given a set of strings, the longest common nonsuperstring problem is finding the longest string that is not a superstring of any string in the given set. It is known that the longest common nonsuperstring problem is solvable in polynomial time. In this paper, we propose an efficient algorithm for the longest common nonsuperstring problem. The running time of our algorithm is linear with respect to the sum of the lengths of the strings in the given set, using generalized suffix trees.

Towards Zero Bit-Error-Rate Physical Unclonable Function: Mismatch-Based vs. Physical-Based Approaches in Standard CMOS Technology

This paper compares two types of physical unclonable function (PUF) circuits in terms of reliability, mismatch-based PUF vs. physical-based PUF. Most previous PUF circuits utilize device mismatches for generating random responses. Although they have sufficient random features, there is a reliability issue that some portions of bits are changed over time during operation or under noisy environments. To overcome this issue, we previously proposed the differential amplifier PUF (DA-PUF) which improves the reliability by amplifying the small mismatches of the transistors and rejecting the power supply noise through differential operation. In this paper, we first report the experimental results with the fabricated chips in a 0.35 μm CMOS process. The DA-PUF shows 51.30% uniformity, 50.05% uniqueness, and 0.43% maximum BER. For 0% BER, we proposed the physical-based VIA-PUF which is based on the probability of physical connection between the electrical layers. From the experimental results with the fabricated chips in a 0.18 μm CMOS process, we found the VIA-PUF has 51.12% uniformity and 49.64% uniqueness, and 0% BER throughout 1,000-time repeated measurements. Especially, we have no bit change after the stress test at 25 and 125 °C for 96 hours.

A simple construction of two-dimensional suffix trees in linear time

The two-dimensional suffix tree of a matrix A is a compacted trie that represents all square submatrices of A. There exists a linear-time construction of two-dimensional suffix trees using the odd-even scheme. This algorithm has the drawback that the merging step is quite complicated. In this paper, we propose a new and simple algorithm to construct two-dimensional suffix trees in linear time by applying the skew scheme to square matrices. To do this, we present a simple algorithm to merge two Isuffix trees in linear time.

Analysis of hardware modular inversion modules for elliptic curve cryptography

Elliptic Curve Cryptography (ECC), one of public-key cryptographic algorithms, is being widely used for device authentication. ECC need heavy computation, and especially modular inversion operation, one of main operations of ECC, is very time-consuming. To improve the performance, hardware implementation can be a solution. There are various modular inversion algorithms, and their performances in hardware module are different from those of software program. In this paper, we implemented various inversion algorithms in hardware, and analyzed them to find out which one is proper for hardware design.