Dong-Woo Jee

A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP

This paper presents a MUlti-SEnsor biomedical IC (MUSEIC). It features a high-performance, low-power analog front-end (AFE) and fully integrated DSP. The AFE has three biopotential readouts, one bio-impedance readout, and support for general-purpose analog sensors The biopotential readout channels can handle large differential electrode offsets ( ±400 mV), achieve high input impedance ( >500 M Ω), low noise ( 620 nVrms in 150 Hz), and large CMRR ( >110 dB) without relying on trimming while consuming only 31 μW/channel. In addition, fully integrated real-time motion artifact reduction, based on simultaneous electrode-tissue impedance measurement, with feedback to the analog domain is supported. The bio-impedance readout with pseudo-sine current generator achieves a resolution of 9.8 m Ω/ √Hz while consuming just 58 μW/channel. The DSP has a general purpose ARM Cortex M0 processor and an HW accelerator optimized for energy-efficient execution of various biomedical signal processing algorithms achieving 10 × or more energy savings in vector multiply-accumulate executions.

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping

A 2 GHz fractional-N digital PLL with a single delay cell, noise shaping ΔΣ TDC is implemented in a 0.13µm CMOS. With a simple structure of Δ modulator followed by a charge pump integrator, a wide range TDC input is converted to ΔΣ modulated bit stream. The implemented TDC consumes 1 mA, and the DPLL shows the in-band phase noise of −107 dBc at 500 kHz offset.

\Delta\Sigma

This paper presents a 1-GHz ΔΣ fractional-N PLL with a noise-filtering scheme using a FIR-embedded phase interpolator. The proposed dual-referenced interpolation scheme compensates for systematic nonlinearity in circuit operation and increases immunity to mismatches in input seed phases. By multiple use of a dual-referenced interpolator, the phase interpolator realizes an embedded FIR filtering for the quantization noise from the ΔΣ modulator. The implemented PLL in 0.13- μm CMOS consumes 16.8 mW and shows a reduction of the phase noise by 34 dB. With 3.2-MHz-wide bandwidth, the proposed filtering technique achieves an in-band noise of -106 dBc at 100 kHz and an out-of-band noise of -107.5 dBc at 6 MHz.

TDC

This paper reports a battery-powered, multi-parameter recording platform with built-in support for concurrent ECG, Bio-Impedance (BIO-Z), Galvanic Skin Response (GSR) and Photoplethysmogram (PPG). The expanded list of dedicated sensor modalities provides a more accurate, more reliable and broader health assessment in wearable electronics. Since data is collected on one chip, precise synchronization between data streams is possible, allowing to use correlation techniques between the data streams. It supports, e.g., research on blood pressure estimation by combining ECG and PPG measurements through pulse arrival time analysis. Combining different sensing modalities like ECG, PPG, and BIO-Z can result in better estimation of hemodynamic parameters, as well as heartbeat and heart-rate variability.

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL

A battery-powered multisensor acquisition system with five dedicated channels [electrocardiograph (50 μW), bioimpedance (46 μW), galvanic skin response (15 μW), and 2× photoplethysmogram (134 μW)] is presented. It includes an ARM Cortex M0, analog and digital filters, timestamp converter and sample rate converter (SRC), and generic interfaces to support additional sensor modalities. The timestamp module makes precise synchronization between the data streams possible. The SRC module makes the sample rates of data from the internal and external sensor readouts compatible with each other, and is up to a factor 35 more energy efficient compared with a software solution. These modules enable performing accurate and reliable (correlation) techniques. The power management includes two buck converters, an LDO, and eight LED drivers, supporting up to 64 LEDs in an 8 × 8 matrix organization. It makes this system the most complete and versatile sensor readout system with state-of-the-art performance (1073 μW with all channels enabled).

28.4 A battery-powered efficient multi-sensor acquisition system with simultaneous ECG, BIO-Z, GSR, and PPG

In the design of a fractional-N PLL, the trade-off between in-band VCO noise and ΔΣ quantization noise constrains the choice of loop bandwidth. Various circuit schemes have been proposed to relax such constrains with noise canceling methods [1, 2] at the cost of significant extra power and chip area, and with FIR filtering techniques [3, 4] utilizing multiple charge pumps (CPs), PFDs and dividers. To reduce the ΔΣ quantization noise, fractional phase rotation [4] has been also a popular approach as an alternative to the dual modulus divider. However, high-resolution phase interpolators (PIs) suffer from nonlinearities due to random mismatches among phase steps and systematic imperfections in circuit operation when the interpolated vector approaches quadrant boundaries, and such nonlinearities eventually limit the amount of noise reduction in PI-based PLL. This work presents a 1GHz ΔΣ fractional-N PLL based on the noise filtering by FIR-embedded PI. The proposed PI scheme greatly improves phase linearity by a dual-referenced interpolation and realizes FIR filtering without using multiple CPs, PFDs, and dividers. The designed fractional-N PLL shows a comparable phase-noise performance to that of an integer-N PLL even with loop bandwidth of 0.1×fref.

A Multi(bio)sensor Acquisition System With Integrated Processor, Power Management,

A 8 GByte/s single-ended parallel transceiver is implemented in a 0.18 mum standard CMOS with a current-balanced pseudo-differential signaling for high-speed memory interface. With a segmented group-inversion coding, 16-bit data is encoded to 20 pins for dramatic reduction of simultaneous switching noise which has been a bottleneck in high-speed parallel links. The proposed pseudo-differential signaling achieves a power-efficient current-mode parallel termination with a reduction of driving current of about 40-percent. For the termination, virtual voltage sources are self-generated by tracking the center of eye opening. The transceiver shows a BER of less than 10-12 at 4 Gb/s/pin.

8 \times 8

This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent ΔΣ time-to-digital converter (TDC) and an infinite impulse response (IIR)-based noise cancellation scheme. The proposed subexponent ΔΣ TDC generates adaptively scaled exponent-only information to track the finest resolution that prevents overloading for a given input environment. In addition, IIR-based noise cancellation provides easy filtering of delta-sigma modulator noise without tightened matching constraints. The DPLL fabricated in 0.13- μm CMOS consumes 8.6 mW and shows the subexponent operation and IIR noise cancellation. The measured phase noise of DPLL is - 98 dBc/Hz at 200-kHz offset and -111 dBc/Hz at 3-MHz offset with 500-kHz loop bandwidth.

LED Drivers, and Simultaneously Synchronized ECG, BIO-Z, GSR, and Two PPG Readouts

This paper presents a new architecture of digitally controlled algorithmic OP amp suitable for scaled CMOS technologies. With inverter-based gain stages and digitally-assisted damping control, the amplifier achieves high-gain and wide input/output ranges even at the minimally allowable supply voltage by digital circuits. The amplifier, implemented in a standard 0.18 mum CMOS, shows a DC gain of 73 dB and 95% settling time of 41 ns at 0.5 V step input.

A 0.1-f ref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering

A digitally controlled operational amplifier (op-amp) with level-crossing-based approximation is proposed. A high gain is effectively obtained by means of a damping control without a stability problem occurring in the multiple gain stages. Compared to the previous version of the zero-crossing-based algorithmic approximation, the proposed scheme further improves the settling time with the class AB operation obtained by switching of multiple driving paths. For verification, the designed op-amp is applied to a 10-bit pipeline ADC and implemented in a 0.18μm CMOS technology. Measured results show that the designed op-amp successfully operates at 10-bit resolution, 10MSample/s pipeline ADC and achieves an effective gain of more than 60dB.