Dong Wu

Electrode-induced digital-to-analog resistive switching in TaO x -based RRAM devices.

In RRAM devices, electrodes play a significant role during the switching process. In this paper, different top electrodes are used for TaO y /Ta2O5-x /AlO σ triple-oxide-layer devices. Top electrode-induced digital resistive switching to analog resistive switching was observed. For Pt top electrode (TE) devices, abrupt digital resistive switching behavior was observed, while Al TE devices showed gradual analog resistive switching behavior. Devices with various AlO σ thicknesses and sizes were fabricated and characterized to evaluate the reliability of the analog resistive switching. The physical mechanisms responsible for this electrode-induced resistive switching behavior were discussed.

Optimization of RRAM-based physical unclonable function with a novel differential read-out method

RRAM-based physical unclonable function (PUF) leveraging the remarkable resistance variability has been proposed and experimentally demonstrated on a 1-kb one-transistor one-resistor array. In this letter, a novel differential read-out method is utilized to reduce the effect of resistance window degradation. The RRAM PUF reliability is optimized through a reliability-enhancement design and oxide stack engineering. The experimental results show that the optimized RRAM PUF demonstrates nearly ideal uniqueness with the inter-chip Hamming distance close to 50%. The reliability of the optimized RRAM PUF is improved over the prior work. The intra-chip Hamming distance is close to the ideal value 0%, which can be sustained for a lifetime of more than ten years at 80 °C. This letter demonstrates that RRAM PUF has great potential for robust lightweight security solutions in IoT applications.

A novel speed-up coding method in quadruple-level-cell 3D NAND flash memory

As more and more demand on high density storage, 3D NAND Flash memories have developed into multi-level cell and triple-level cell. With the charge-trapping technology adopted in 3D NAND Flash, it is possible to achieve quadruple-level-cell (QLC) which brings higher density capability. Meanwhile, the program coding method makes significant impact on the efficiency of the lockout operation in the program verification. A novel speed-up coding method is presented in this paper, which reduces nearly 30% time delay and 40% power consumption during the verify lockout operation in the QLC memory.

Uniformity improvements of low current 1T1R RRAM arrays through optimized verification strategy

This paper systematically analyzed and optimized the operation parameters of low current 1T1R RRAM arrays. Considering both thermal and electrical field driven effects, a current and voltage joint verification strategy has been proposed. Highly uniform multilevel resistive switching performances with LRS resistance higher than 100kΩ and HRS resistance higher than 10MΩ were obtained on 130nm CMOS process fabricated 1T1R RRAM arrays using the optimized verification strategy.

Optimization of writing scheme on 1T1R RRAM to achieve both high speed and good uniformity

This paper systematically analyzed the tradeoff between writing operation time and tail bit of LRS, and provided the optimal writing operation time for 1T1R RRAM with the target LRS 500kn and HRS 10Mn. Under three different cases of pulse width, the experiment results all show that the optimal voltage amplitude and step could achieve a good tradeoff between writing operation time and tail bits of LRS. Based on the analysis of three kinds of pulse width, we find that the verification operation strategy using the smallest pulse width (10ns) shows the best performances. The RESET process needs three pulses and SET process needs four pulses at most. And the tail bit rate is lower than 7%. The related voltage overshoot effect on the pulse rising edge was discussed to explain the origin that the short pulse width is superior to long pulse width.

A high precision threshold voltage readout method for flash memory

A readout circuit for flash memory threshold voltage distribution is proposed in this paper. This circuit includes ramp generator circuit, comparator and 9-bit counter which converts threshold voltage into digital outputs. Besides, word line and bit line decoder, high voltage generator, bias module and timing control circuit are integrated as peripheral circuit. This chip is fabricated by 0.13 μm 2P3M NOR flash memory process with 128Mb cells. The experimental results show that this readout circuit can depict threshold voltage distribution accurately. Additionally, it also can be used to analysis discreteness of memory cells and improve program/erase algorithms.

A high speed low power negative sensing architecture for 3D NAND Flash memory

A new sensing architecture aiming at negative threshold voltage detection for 3D NAND Flash memory cells is proposed. This sensing architecture does not need triple well devices and negative voltage supplies. In this architecture, we apply 2 V to source line (SL) rather than 0V which is always used in conventional method. We prove that this architecture is feasible by Technology Computer Aided Design (TCAD) simulation. We have also designed a sense amplifier (SA) to support the proposed sensing architecture. This SA has advantages including lower noise, 9.4% faster read speed, and 51.6% lower power consumption compared to the conventional counterpart.

A 16 Mb RRAM test chip based on analog power system with tunable write pulses

One transistor one resistor (1T1R) structure can be used to suppress the sneak current in RRAM array. In this paper, a 16Mb 1T1R RRAM chip is proposed. The 130 nm HH-Grace process is used as the FEOL of the chip. A HfOx/CMO based RRAM stack will be fabricated using back end process. The chip mainly contains four blocks: the RRAM array, the analog power block, the control logic block and the pad ring which uses standard pad provided by foundry. The operating conditions is designed to be configurable to explore different RRAM stack. Tunable write pulses can be used to improve the RRAM performance. The analog power system supplies different voltage levels to achieve specific function. The simulation results show that the chip can work as expected.