Dong-Yong Kim

Multilevel monolithic 3D inductors on silicon

This paper has been the analysis of passive devices in Si RF and microwave. Multilevel monolithic 3D inductors implemented in a standard CMOS technology are presented. Since on-chip inductors are constrained to be planar, the typical solution is to form a spiral. Proposed inductors are composed of 3D structures requiring no extra processing steps. Inductances are higher in increasing the mutual inductance besides the self-inductance. In this reason, this structure gives rise to a quality factor Q and a inductance using 3D geometry in small areas.

A modified elliptic function with diminishing ripples

A modified elliptic low-pass filter function is proposed. The modified elliptic function possesses progressively diminishing ripples in both passband and stopband, and improves the frequency and the time-domain characteristics as compared with the classical elliptic function. Also it is realizable in the doubly-terminated ladder structures for the order n even or odd, thus lending themselves amenable to high-quality active RC or switched capacitor filters through simulation techniques.

The design and comparison of elliptic filters with an OTA-C structure

A CMOS operational transconductance amplifier and capacitor (OTA=C) integrator which is used for high-frequency operation has been designed and simulated by the SPICE 2G program. The authors have realized the continuous-time OTA=C elliptic low-pass filters by a cascade method and a signal flow graph (SFG) method using only capacitors and OTAs. The frequency characteristics of the OTA=C filters are compared.<<ETX>>

Design of oversampling sigma-delta DAC for ADSL applications

A transceiver for ADSL systems contains an interpolated combfilter, halfband filters, oversampling sigma delta modulator, a current steering DAC and an analog filter. The circuit complexity of the architecture makes it necessary to use behavioral models to determine the system features. For this reason, we need a specific behavioral simulation environment using the Matlab program. The Matlab is crucial for these circuits to be rapidly incorporated in larger systems, in particular in the context of mixed-signal-test schemes. Design trade-off among the blocks has also been discussed. The design methodology is based on behavioral design and CMOS process.

Wideband multi-bit third-order sigma-delta ADC for wireless transceivers

This paper presents a multi-bit sigma-delta data converter with third-order 3-bit topology. This converter can achieve high resolution with a lower order modulator and lower oversampling ratio than single-bit converter. The dynamic element matching (DEM) algorithm is designed in such a way as to minimize delay within the feedback loop of the sigma-delta ADC. The behavioral model is used to simulate the designed sigma-delta data converter. The designed ADC achieves 14-bit resolution, a peak SNR of 87dB within a 1 MHz signal baseband at a clock rate of 50MHz.This paper presents a multi-bit sigma-delta data converter with third-order 3-bit topology. This converter can achieve high resolution with a lower order modulator and lower oversampling ratio than single-bit converter. The dynamic element matching (DEM) algorithm is designed in such a way as to minimize delay within the feedback loop of the sigma-delta ADC. The behavioral model is used to simulate the designed sigma-delta data converter. The designed ADC achieves 14-bit resolution, a peak SNR of 87dB within a 1 MHz signal baseband at a clock rate of 50MHz.

Some prominent characteristics of the modified inverse Chebyshev function

The modified inverse Chebyshev function exhibits progressively diminishing ripples in the stopband. The modified inverse Chebyshev function can be realizable using the doubly-terminated ladder network for the order n even or odd. Besides the doubly-terminated ladder network realizability, lower pole-Q values of the modified inverse Chebyshev function are accountable for improved time delay characteristic, preferable time domain performance, and low pole-Q sensitivity as compared with the classical inverse Chebyshev function.

Design of CMOS composite transistors with improved operating region

Proposes two new CMOS composite transistors with an improved operating region by reducing a threshold voltage. The proposed composite transistors 1 and 2 employ a p-type folded composite transistor and an electronic Zener diode in order to decrease the threshold voltage, respectively. The simulation has been carried out using 0.25/spl mu/m n-well process with 2.5V supply voltage.

The design of the high speed amplifier circuit for using in the analog subsystems

A high-speed CMOS amplifier circuit has been designed and applied in a high-speed simple CMOS comparator. The designed CMOS amplifier circuit has a new architecture for use in high-speed analog subsystem circuits. This architecture is composed of internal biasing circuits and a CMOS complementary gain stage and has improved gain and speed characteristics. A high speed simple CMOS comparator using an improved CMOS amplifier circuit with a standard 1.5 mu m processing parameter has been designed. This circuit can be operated in a few nanoseconds.<<ETX>>