Donghui Guo

Efficient implementation for MD5-RC4 encryption using GPU with CUDA

Benefit from the novel Compute Unified Device Architecture (CUDA) introduced by NVIDIA, Graphics Processing Unit (GPU) turns out to be a promising solution for cryptography applications. In this paper we present an efficient implementation for MD5-RC4 encryption using NVIDIA GPU with novel CUDA programming framework. The MD5-RC4 encryption algorithm was implemented on NVIDIA GeForce 9800GTX GPU. The performance of our solution is compared with the implementation running on an AMD Sempron Processor LE-1200 CPU. The results show that our GPU-based implementation exhibits a performance gain of about 3–5 times speedup for the MD5-RC4 encryption algorithm.

Speaker recognition using weighted dynamic MFCC based on GMM

In this paper, a new algorithm of feature parameter extraction is proposed for application in speaker recognition system, which combines the traditional MFCC and the dynamic MFCC as a new series of coefficients. According to the statistics analysis of the different contribution by the dynamic MFCC and traditional MFCC, these coefficients are weighted as front-end parameters of the GMM, which would decrease the dimension of the mixed weighted GMM and reduce the computation complexity. The experiments based on the TIMIT and VOA speech database were implemented in MATLAB environment, and the results showed the speaker recognition system with the Weighted Dynamic MFCC could obtain better performance with high recognition rate and low computational complexity.

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow

High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture (CUDA), enables efficient description and implementation of independent computation cores. HLS tools can effectively translate the many threads of computation present in the parallel descriptions into independent, optimized cores. The generated hardware cores often heavily share input data and produce outputs independently. As the number of instantiated cores grows, the off-chip memory bandwidth may be insufficient to meet the demand. Hence, a scalable system architecture and a data-sharing mechanism become necessary for improving system performance. The network-on-chip (NoC) paradigm for intrachip communication has proved to be an efficient alternative to a hierarchical bus or crossbar interconnect, since it can reduce wire routing congestion, and has higher operating frequencies and better scalability for adding new nodes. In this paper, we present a customizable NoC architecture along with a directory-based data-sharing mechanism for an existing CUDA-to-FPGA (FCUDA) flow to enable scalability of our system and improve overall system performance. We build a fully automated FCUDA-NoC generator that takes in CUDA code and custom network parameters as inputs and produces synthesizable register transfer level (RTL) code for the entire NoC system. We implement the NoC system on a VC709 Xilinx evaluation board and evaluate our architecture with a set of benchmarks. The results demonstrate that our FCUDA-NoC design is scalable and efficient and we improve the system execution time by up to 63× and reduce external memory reads by up to 81% compared with a single hardware core implementation.

A New Wavelet Watermark Scheme of Color Image Based on Chaotic Sequences

A novel transform-domain image watermark based on chaotic sequences is proposed in this paper. A complex chaos-based scheme is developed to embed a gray-level image in the wavelet domain of the original color image signal. The chaos system plays an important role in the security and invisibility of the proposed scheme. The parameter and initial state of chaos system directly influence the generation of watermark information as a key. Meanwhile, the watermark information has the property of spread spectrum signal by chaotic sequence. To improve the invisibility of watermarked image Computer simulation results show that the proposed algorithm is imperceptible and is robust to most watermarking attacks, especially to image cropping, JPEG compression and multipliable noise.

Design of 16-bits constant-current LED driver

A 16-bits Constant-Current LED Driver Integrated Circuit (abbreviated as “Driver”) is presented in this paper. It is fabricated with 0.6-µm 2P3M CMOS process in an active area of 0.9mm × 0.9mm. The driver provides 16 open-drain, constant current sinking LED driver outputs. All the constant-current outputs are programmed together by a signal external resistor. Post simulation result shows that each output channel provides constant current up to 70mA within possible temperature range of −40°C to 125°C and power supply range of 3V to 5.5V. The current match between each bit is 3% and between each technical corner is less than 6% typically. More importantly, it includes the power-on reset and over-heating protection circuits, which help protect the IC against logic error and burnt up.

A new images hiding scheme based on chaotic sequences

We propose a data hidding technique in a stilt image. This technique is based on chaotic sequence in the transform domain of covert image. We use different chaotic random sequences multiplied by multiple sensitive images, respectively, to spread the spectrum of sensitive images. Multiple sensitive images are hidden in s covert image as a form of noise. The results of theoretical analysis and computer simulation show the new hiding technique have better properties with high security, imperceptibility and capacity for hidden information in comparison with the conventional scheme such as LSB (Least Significance Bit).We propose a data hidding technique in a still image. This technique is based on chaotic sequence in the transform domain of cover image. We use different chaotic random sequences multiplied by multiple sensitive images, respectively, to spread the spectrum of sensitive images. Multiple sensitive images are hidden in a covert image as a form of noise. The results of theoretical analysis and computer simulation show the new hiding technique have better properties with high security, imperceptibility and capacity for hidden information in comparison with the conventional scheme such as LSB (Least Significance Bit).

Efficient architectures of MDCT/IMDCT implementation for MPEG audio codec

Efficient architectures for realizing MDCT/IMDCT are presented. Based on the symmetry property of trigonometric functions, N-point MDCT formula will be transferred into an odd-even index paralleling process which can be achieved by two different types of decomposition, recursive formed DCT-II kernel or FFT-based DCT-IV kernel. Then a butterfly unit is employed to accelerate the computational speed. Furthermore, these new architectures are suitable for the computations of both MDCT and IMDCT, which improve the hardware efficiency. For verification, an experiment of MPEG2 AAC using this optimized FFT-based MDCT architecture on Altera Stratix FPGA is implemented. The analyzed results show the proposed structure provides a superior performance in terms of the computation rate, the data throughput and the hardware utilization. In addition, these MDCT/IMDCT architectures can be employed in many international audio standard systems.

A new method of test data generation for branch coverage in software testing based on EPDG and Genetic Algorithm

A new method called EPDG-GA which utilizes the Edge Partitions Dominator Graph (EPDG) and Genetic Algorithm (GA) for branch coverage testing is presented in this paper. First, a set of Critical Branches (CBs) are obtained by analyzing the EPDG of the tested program, while covering all the CBs implies covering all the branches of the Control Flow Graph (CFG). Then, the fitness functions are instrumented in the right position by analyzing the Pre-Dominator Tree (PreDT), and two metrics are developed to prioritize the CBs. Coverage-Table is established to record the CBs information and keeps track of whether a branch is executed or not. GA is used to generate test data to cover CBs so as to cover all the branches. The comparison results show that this approach is more efficient than random testing approach.

A path-oriented test data generation approach for automatic software testing

The clonal selection (CS) algorithm is an optimization algorithm based upon the clonal selection principle in the biological immune system. This paper presents a novel approach that uses CS algorithm for path-oriented test data generation. The approach takes a selected path as a target and executes sequences of operators iteratively for test case to generate. An affinity function which is made up of a similarity and penalty value is developed to guide the test generator to make successive modifications of the test data, so that test data can ever closer to satisfy the requirement. The comparison results show that this approach is more efficient than those based on other heuristic algorithms in finding solutions.

Auto-focusing system for microscope based on computational verb controllers

In this paper, an auto-focusing system of microscope for integrated circuits (IC) analysis is presented. In this system, the Laplacian algorithm is used as the evaluation function, which provides a reference to the degree of defocus. The auto-focusing controlling algorithm based on computational verb theory consists of two controllers designed: the moving-speed controller and the moving-direction controller. Both controllers work well under the verb-control rules designed in this paper. It has shown that the system can focus accurately and quickly, and it can adjust itself when it is out of focus.