Dongliang Zhang

Al2O3–Gd2O3 double-films grown on graphene directly by H2O-assisted atomic layer deposition

We demonstrate the direct Al2O3–Gd2O3 double-films growth on graphene by H2O-assisted atomic layer deposition (ALD) using a hexamethyl disilazane precursor {Gd[N(SiMe3)2]3}. No defects are brought into graphene as shown by Raman spectra; the surface root-mean-square (RMS) roughness of the Al2O3–Gd2O3 double-films is down to 0.8 nm, comparable with the morphology of pristine graphene; the films are compact and continuous, and the relative permittivity is around 11, which indicate that H2O-assisted ALD can prepare high quality dielectric films on graphene.

Interface engineering of an AlNO/AlGaN/GaN MIS diode induced by PEALD alternate insertion of AlN in Al2O3

In this paper, AlNO nano-films have been deposited on an AlGaN/GaN heterojunction by alternating growth of AlN and Al2O3 using plasma enhanced atomic layer deposition (PEALD). With optimized AlN layer insertion in Al2O3, the oxygen is effectively blocked from diffusing to the AlGaN surface and the formation of detrimental Ga–O bonds is significantly suppressed. Owing to the negative fixed charges in Al2O3, provided by the incorporated nitrogen, the flat band voltage (Vfb) of the AlNO/AlGaN/GaN metal–insulator–semiconductor (MIS) diode exhibits a positive shift of 1.50 V, compared with the Al2O3/AlGaN/GaN MIS diode. Markedly reduced hysteresis and frequency-dispersion in the C–V characteristics have also been observed at the AlNO/AlGaN interface. Furthermore, the interface states density (Nit) at the AlNO/AlGaN interface has been reduced by one order of magnitude compared with the Nit at the Al2O3/AlGaN interface, and the border traps density (Nbt) near the AlNO/AlGaN interface is also identified to be reduced by the insertion of AlN layers into Al2O3. The PEALD induced optimization of AlNO deposition on the AlGaN/GaN heterojunction provides a pathway to the fabrication of AlGaN/GaN high electron mobility transistors (HEMTs) with low interface trap density.

Negative differential resistance in the I–V curves of Al2O3/AlGaN/GaN MIS structures

Negative differential resistance (NDR) induced by inter-valley electron transfer is often observed in Gunn diodes. In this paper, we report the observation of this novel NDR phenomenon in Al2O3/AlGaN/GaN metal–insulator–semiconductor (MIS) structures. This study offers new understanding on the gate characteristics of GaN HEMTs. The NDR is found to be more prominent at low temperature. The voltage (VNDR) at the onset of the NDR is temperature dependent and decreases with temperature. Measurement results support the possibility that the NDR originates from the inter-valley electron transfer in conjunction with tunneling. The fitting results of the measured I–V with tunneling models reveal that TAT (trap assisted tunneling) is the dominating mechanism at low gate bias and FNT (Fowler–Nordheim tunneling) is dominant at relatively high gate voltage. Moreover, the energy difference between valley Γ and valley M–L in the GaN conduction band can be estimated by the voltage (VNDR), which is linearly related to the crystal temperature.

Performance Improvement and Current Collapse Suppression of Al 2 O 3 /AlGaN/GaN HEMTs Achieved by Fluorinated Graphene Passivation

In this letter, fluorinated graphene (FG) is utilized to passivate GaN surface for a metal–insulator–semiconductor high electron mobility transistor (MIS HEMT). The FG-MIS HEMT achieves better DC characteristics than a traditional MIS HEMT, including larger saturation drain current density (34.3%), higher peak trans-conductance (14.4%), lower ON-resistance (21.6%), and lower off-state leakage. Moreover, current collapse measurement reveals that not only can FG suppress the drain saturation current reduction of MIS HEMT from 41.8% to 8.1% at off-state drain bias of 50 V, but also it prevents dynamic ON-resistance increasing with off-state stress. The coverage of FG on GaN surface can prevent GaN being oxidized and N diffusion from GaN during gate dielectric deposition, thus suppressing the formation of Ga-O bonds and Ga dangling bonds, leading to an excellent interface condition for Al2O3/GaN with reduced fixed interface charges. Therefore, significant passivation effect is achieved.

Semiconductor-like nanofilms assembled with AlN and TiN laminations for nearly ideal graphene-based heterojunction devices

As a new class of electronic devices, graphene heterojunctions in which graphene is combined with bulk or other layered 2D semiconductors have been realized. However, due to the restriction of available manufacturing, the substrates should be the bulk semiconductors adopted in graphene–semiconductor heterojunctions, limiting graphene-based heterojunction fabrication only on a few finite substrates. In addition, in order to lower the on-resistance, more fabrication processes such as etching poly-filled trenches and filling with silicon oxide should be performed. To solve the limitation, other 2D semiconductors such as MoS2 and WS2, which can be deposited on a variety of substrates, have been utilized to form heterojunctions with graphene. Nevertheless, wafer-scale MoS2 or WS2 growth is still a critical issue. Here we perform the plasma-enhanced atomic layer deposition (PEALD) technique to assemble AlN and TiN and achieve a semiconductor-like AlTiN nanofilm. In addition, the semiconductor-like AlTiN nanofilm is combined with graphene to fabricate a vertical heterojunction device, which has an ideality factor down to 1.13, close to the best reported ideality factor (1.08) of graphene heterojunctions. The current on–off ratio is up to 105 dispensing with any gate bias voltage under ambient conditions. The graphene–AlTiN heterojunction devices are compatible with a variety of substrates and can be applied to large-scale and power-efficient electronics.

Decreasing graphene synthesis temperature by catalytic metal engineering and thermal processing

Chemical vapor deposition (CVD) from gaseous hydrocarbon sources has shown great promise for large-scale graphene growth, but the high growth temperature, typically 1050 °C, requires precise and expensive equipment and makes the direct deposition of graphene in electronic device manufacturing processes unfeasible due to the severe physical damage to substrates. Here we demonstrate a facile route to synthesize graphene by catalytic metal engineering and thermal processing. The engineered catalytic metal (copper) with carbon implantation could lower the synthetic temperature to 700 °C. And the resulting graphene shows few defects, uniform morphology and high carrier mobility, comparable to CVD graphene grown at 1050 °C. This technique could expand the applications of graphene in electronic and optoelectronic device manufacturing and is compatible with conventional microelectronics technology.

PEALD induced interface engineering of AlNO/AlGaN/GaN MIS diode with alternate insertion of AlN in Al 2 O 3

Atomic layer deposited Al<inf>2</inf>O<inf>3</inf> is an industry-accepted gate dielectric used in the AlGaN/GaN MIS-HEMT structure, but direct deposition of Al<inf>2</inf>O<inf>3</inf> on AlGaN/GaN will lead to the formation of detrimental Ga-O bonds, resulting in high-density interface traps. In this work, alternate AIN incorporation in Al<inf>2</inf>O<inf>3</inf> to form AINO nano-films is proposed to suppress the gate leakage current and reduce interface trap density. In addition, nitrogen can incorporate on either cation/anion sites or interstitial sites and thus becomes a source of negative fixed charges within Al<inf>2</inf>O<inf>3</inf>, which can contribute to positive shifting of flat band voltage (V<inf>fb</inf>).