Dongmin Park

Design Techniques for a Low-Voltage VCO With Wide Tuning Range and Low Sensitivity to Environmental Variations

This paper presents design techniques for a low-voltage voltage-controlled oscillator (VCO) with a wide tuning range and low sensitivity to process, voltage, and temperature (PVT) variations. For wide tuning range, a switched tuning scheme is employed coupled with voltage-boosting techniques in a manner that improves the quality factor and tuning range of a switched capacitor array. To minimize the design overhead required for a robust VCO, an adaptive body-biasing technique is proposed, which relaxes the startup constraint and increases the VCOs immunity to PVT variations. The proposed VCO is implemented in 0.18-mum CMOS technology and operates at 2.4 GHz. It achieves phase noise of - 117 dBc/Hz at 1-MHz offset and a tuning range 20% while consuming 365 muW of power. The figure-of-merit with the tuning range is -197 dBc/Hz, which is the lowest among recent state-of-the-art low-voltage VCOs.

A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL

This paper presents a nested-PLL architecture for a low-noise wide-bandwidth fractional-N frequency synthesizer. In order to reduce the quantization noise, operating frequency of ΔΣ modulator (DSM) is increased by using an intermediate output of feedback divider. A PLL which serves as an anti-alias filter is added to suppress noise aliasing caused by the divider. Prototype implemented in a 0.13 μm CMOS using ring VCOs achieves 26.3 dB of quantization noise suppression while consuming 15.2 mW and occupying 0.17 mm2.

An Adaptive Body-Biased VCO with Voltage-Boosted Switched Tuning in 0.5-V Supply

This paper presents an adaptive body-biased low-voltage VCO. Despite the 0.5-V supply, the VCO uses coarse digital tuning by employing voltage-boosting technique. In addition, the effect of PVT variations is reduced by adaptive body-biasing technique. The proposed VCO is implemented in 0.18 mum CMOS technology and operates at 2.4 GHz. It achieves phase noise of -115.8 dBc/Hz at 1-MHz offset and 7.3 % of tuning range, while consuming 200 muW. Figure-of-merit with the tuning range is -189.1 dBc/Hz, which is the lowest among the recent state-of-the-art low-voltage VCOs

A 1.8 V 900

This letter presents a charge-recycling VCO and divider in 0.18 mum CMOS technology. The power consumption of the proposed circuit is significantly reduced by stacking the low-voltage divider on the top of the low-voltage VCO, and hence, the VCO reuses the current from the divider. To enhance the reliability of the proposed circuit under supply voltage variation, transistor sharing and adaptive body-biasing techniques are employed. It allows the proposed circuit to operate down to 1.45 V of supply voltage without degrading the FoM. Experimental results show that the proposed circuit achieves 900 muW of power consumption and -184 dBc/Hz of FoM at 1.8 V.

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A 1.2 V 2.5 GHz 860 muW fractional-N synthesizer is implemented in 130 nm CMOS. It employs charge recycling technique for implicit DC-DC conversion without using any voltage regulators, and achieves -77dBc/Hz and -113.5 dBc/Hz of phase noise at 100 kHz and 1MHz offset, respectively. Self-biased divider and VCO enables robust operation of the proposed circuit.

W 4.5 GHz VCO and Prescaler in 0.18

A power-optimized low-voltage VCO with wide tuning range is proposed. The VCO achieves low power by optimum selection of inductance in the L-C tank. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosted digital tuning technique. It is shown that the power consumption of VCO with a required output swing and phase noise can be minimized if the inductance is chosen such that its LQ and Q/L is maximized. To increase the tuning range, a digital tuning method is used where the output voltage of the VCO is exploited to generate a high voltage for the switches in the digital tuning scheme. The proposed VCO achieves phase noise of -120 dBc/Hz at 1-MHz offset and 18 % tuning range while consuming 660 muA in 0.5-V supply. Figure-of-merit with tuning range of the proposed VCO is -197.1 dB, which is the lowest among the recent state-of-the-art low-voltage VCOs

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In this letter, a fractional-N frequency synthesizer based on an offset phase-locked loop (OPLL) architecture is presented. The proposed synthesizer achieves low-noise as the two low-pass filters that are inherent in the OPLL highly suppresses the quantization noise from the delta-sigma modulator. In addition, it consumes low power by employing charge-recycling technique in the sub-PLL. A prototype synthesizer implemented in 0.13 μm CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of power.

m CMOS Using Charge-Recycling Technique

Fractional-N PLLs [1-3] are widely used due to their fine frequency resolution. However, their phase noise performance is typically worse than the integer-N [4, 5, 6] counterpart due to the quantization noise of the delta-sigma modulator (DSM). In this paper, we propose a low-noise fractional-N PLL that achieves best-case figure-of-merit (FOM) of -240.3dB, rms jitter of 255fsrms and worst-case fractional spur of -53.9dBc by using an 800MHz reference generated from a low-noise reference-injected integer-N PLL.

A 2.5-GHz 860μW charge-recycling fractional-N frequency synthesizer in 130nm CMOS

A nested-PLL(NPLL) architecture for low-noise wide-bandwidth fractional-N frequency synthesizer is presented. In order to reduce the quantization noise of the fractional-N PLL, delta-sigma modulator(DSM) is clocked at nine times of the reference frequency. A band pass filter, implemented in form of a PLL, is added to reduce the noise folding. Prototype implemented in 0.13um CMOS process achieves 26dB quantization noise suppression while consuming 9.6mW and occupying 0.46mm2.

A power-optimized CMOS LC VCO with wide tuning range in 0.5-V supply

Ultra-low power frequency synthesizers resilient to environmental variations are desired in various wireless microsensor applications where power consumption and reliability are important performance metrics. This paper reviews the design techniques for a ultra-low power PLLs employing low-supply voltage and charge recycling techniques. Design challenges such as minimizing sensitivity to environmental variations are addressed for low-voltage and charge-recycling operation, which include adaptive body-biasing and implicit negative feedback DC-DC conversion.