Dongsub Choi

Optimization of High Order Control including overlay, alignment and sampling

Overlay requirements for semiconductor devices are increasing faster than anticipated. Overlay becomes much harder to control with current methods and therefore novel techniques are needed. In this paper, we present our investigation methods for High Order Control, and the candidates for improvement. This paper will present the study for each components of high order control. High order correction is one component for high order control and several correction methods were compared for this study. High order alignment is another important component for higher order control instead of using conventional linear model for the alignment. Alignment and overlay measurement sampling decision becomes a more critical issue for sampling efficiency and accuracy. Optimal sampling for high order was studied for high order control. Using all these studies, various applications for optimal high order control have also been studied. This study will show the general approach for high order control with theory and actual experimental data.

Device-correlated metrology for overlay measurements

Abstract. One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.

Investigation on accuracy of process overlay measurement

The shrinkage of design rule necessitated corresponding tighter overlay control. However, in advanced applications, the extension of current technology may not be able to meet the control requirement, consequently, additional breakthroughs are required. In this study, we investigated methods to enhance the overlay control, approaches by extraction of real overlay error out of overlay measurement. So far, only the destructive inspections like vertical SEM have enabled us to measure real misalignment. But, a concept of non-destructive method is proposed in this paper, extracting vertical information from the results of multiple measurements with various measurement conditions, keys or recipes. With this proposed method, the measurement accuracy can be improved and we can enable a new knob for overlay control.

DCM: device correlated metrology for overlay measurements

One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (OVL) targets and actual device overlay error. In this study, we introduce the concept of Device Correlated Metrology (DCM), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking CD-SEM (Critical Dimension – Scanning Electron Microscope) target. The hybrid OVL target is designed to accurately represent the process influence found on the real device. In the general case, the CD-SEM can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of CD-SEM measurement uncertainty. Direct OVL measurements by CD-SEM show excellent correlation with optical OVL measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based OVL metrology methods using AIM or AIMid OVL targets, and scatterometry-based overlay methods such as SCOL (Scatterometry OVL). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.

Mask registration impact on intrafield on-wafer overlay performance

Improved overlay performance is one of the critical elements in enabling the continuing advancement of the semiconductor integrated circuit (IC) industry. With each advancing process node, additional sources of overlay error and new methods of reducing those errors need to be taken into account. We consider the impact of mask registration or pattern placement errors on intra-field on-wafer overlay performance. Mask registration data is typically minimally sampled and not well incorporated into the wafer fab overlay systems. In this work we consider mask-to-mask overlay and point out the importance of high density sampling as well as the potential for improved mask qualification and disposition.

Lithography aware overlay metrology target design method

We present a metrology target design (MTD) framework based on co-optimizing lithography and metrology performance. The overlay metrology performance is strongly related to the target design and optimizing the target under different process variations in a high NA optical lithography tool and measurement conditions in a metrology tool becomes critical for sub-20nm nodes. The lithography performance can be quantified by device matching and printability metrics, while accuracy and precision metrics are used to quantify the metrology performance. Based on using these metrics, we demonstrate how the optimized target can improve target printability while maintaining the good metrology performance for rotated dipole illumination used for printing a sub-100nm diagonal feature in a memory active layer. The remaining challenges and the existing tradeoff between metrology and lithography performance are explored with the metrology target designer’s perspective. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.

Overlay control methodology comparison: field-by-field and high-order methods

Overlay control in advanced integrated circuit (IC) manufacturing is becoming one of the leading lithographic challenges in the 3x and 2x nm process nodes. Production overlay control can no longer meet the stringent emerging requirements based on linear composite wafer and field models with sampling of 10 to 20 fields and 4 to 5 sites per field, which was the industry standard for many years. Methods that have emerged include overlay metrology in many or all fields, including the high order field model method called high order control (HOC), and field by field control (FxFc) methods also called correction per exposure. The HOC and FxFc methods were initially introduced as relatively infrequent scanner qualification activities meant to supplement linear production schemes. More recently, however, it is clear that production control is also requiring intense sampling, similar high order and FxFc methods. The added control benefits of high order and FxFc overlay methods need to be balanced with the increased metrology requirements, however, without putting material at risk. Of critical importance is the proper control of edge fields, which requires intensive sampling in order to minimize signatures. In this study we compare various methods of overlay control including the performance levels that can be achieved.

Multi-level overlay techniques for improving DPL overlay control

Overlay continues to be one of the key challenges for lithography in semiconductor manufacturing, especially in light of the accelerated pace of device node shrinks. This reality will be especially evident at 20nm node where DPL and multi-layer overlay will require 4nm or less in overlay control across many critical layers in order to meet device yield entitlements. The motivation for this paper is based on improving DPL overlay control in face of the high complexity involved with multi-layer overlay requirements. For example, the DPL-2nd-litho layer will need to achieve tight registration with the DPL-1st-litho layer, and at the same time, it will need to achieve tight overlay to the reference-litho layer, which in some cases can also be a DPL layer. Of course, multi-level overlay measurements are not new, but the combination of increased complexity of multi-DPL layers and extremely challenging overlay specifications for 20nm node together will necessitate a better understanding of multi-level overlay control, specifically in terms of root cause analysis of multi-layer related overlay errors and appropriate techniques for improvement In this paper, we start with the identification of specific overlay errors caused by multi-layer DPL processing on full film stack product wafers. After validation of these findings with inter-lot and intra-lot controlled experiments, we investigate different advanced control techniques to determine how to optimize overlay control and minimize both intra-lot and inter-lot sources of error. A new approach to overlay data analysis will also be introduced that combines empirical data with target image quality data to more accurately determine and better explain the root cause error mechanism as well as provide effective strategies for improved overlay control.

The study and simulation of high-order overlay control including field-by-field methodologies

Overlay continues to be one of the key challenges for photolithography in semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. The corresponding tighter overlay specs require the consideration of new paradigms for overlay control, such as high-order control schemes and/or field-by-field overlay control. These approaches have been demonstrated to provide tighter overlay control for design rule structures, and can be applied to areas such as double patterning lithography (DPL), as well as for correcting non-linear overlay deformation signatures caused by non-lithographic wafer processing. Previously we presented a study of high-order control applied to high order scanner correction, high order scanner alignment, and the sampling required to support these techniques. Here we extend this work, using sources of variation (SOV) techniques, and have further studied the impact of field by field compensation. This report will show an optimized procedure for high order control using production wafers and field by field control.

Sampling for advanced overlay process control

Overlay metrology and control have been critical for successful advanced microlithography for many years, and are taking on an even more important role as time goes on. Due to throughput constraints it is necessary to sample only a small subset of overlay metrology marks, and typical sample plans are static over time. Standard production monitoring and control involves measuring sufficient samples to calculate up to 6 linear correctables. As design rules shrink and processing becomes more complex, however, it is necessary to consider higher order modeled terms for control, fault detection, and disposition. This in turn, requires a higher level of sampling. Due to throughput concerns, however, careful consideration is needed to establish a base-line sampling, and higher levels of sampling can be considered on an exception-basis based on automated trigger mechanisms. The goal is improved scanner control and lithographic cost of ownership. This study addresses tools for establishing baseline sampling as well as motivation and initial results for dynamic sampling for application to higher order modeling.