Douglas Niehaus

Programming models for hybrid FPGA-cpu computational components: a missing link

Emerging hybrid chips containing cpu and FPGA components are an exciting new development promising commercial off-the-shelf economies of scale, while also supporting hardware customization.

A firm real-time system implementation using commercial off-the-shelf hardware and free software

The emergence of multimedia and high-speed networks has expanded the class of applications that combine the timing requirements of hard real-time applications with the need for operating system services typically available only on soft-real time or time-sharing systems. These applications, which the authors describe as firm real-time, currently have no widely-available, low-cost operating system to support them. They discuss modifications they have made to the popular Linux operating system that give it the ability to support the comparatively stringent timing requirements of these applications, while still giving them access to the full range of Linux services. Using their firm real-time system as a basis, they have developed the ATM Reference Traffic System (ARTS) that is capable of recording and accurately reproducing packet-level ATM traffic streams with timing resolution in microseconds. The effectiveness of this application, as well as the comparative ease with which it was developed illustrate the performance and utility of the system.

Programming models for hybrid CPU/FPGA chips

Designers of embedded and real-time systems are continually challenged to meet tighter system requirements at better price-performance ratios. Best-practice methods have long promoted the use of commercial-off-the-shelf components to reduce design costs and time to market, but creating COTS components that are reusable in a wide range of applications remains difficult. In part, the challenge lies in satisfying the contradictory design forces of generalization and specialization. Systems designers are all too familiar with the tension these opposing forces cause in trying to balance cost versus performance. Adopting COTS components reduces costs and time to market but often fails to meet the most demanding performance requirements; custom-designed components can achieve significantly higher performance but at greater development costs and longer times to market. Emerging hybrid chips containing both CPU and field-programmable gate array (FPGA) components are an exciting new development. They promise COTS economies of scale while also supporting significant hardware customization. Components that combine a CPU and reconfigurable logic gates need a programming model that abstracts the computational hardware.

Performance benchmarking of signaling in ATM networks

The overhead associated with establishing switched virtual circuits (SVCs) in high-speed wide area ATM networks is an important performance factor in applications with client/server architectures, including the World Wide Web and low-latency applications such as command/control and modeling/simulation. This article quantifies this overhead by describing a benchmarking framework implemented in a reliable, portable, and easily expandable toolset designed to conduct measurements of well-defined parameters and performance metrics on equipment that is either isolated or connected to a live network. The usefulness of this toolset is then demonstrated in a test suite applied to assess call rates and connection establishment latency of point-to-point and point-to-multipoint ATM connections in the MAGIC, ATDnet, and AAI WANs, on the campus ATM LAN at NRL, and on individual switches in our laboratories.

The Spring System: Integrated Support for Complex Real-TimeSystems

The Spring system is a highly integrated collection of software and hardware that synergistically operates to provide end-to-end support in building complex real-time applications. In this paper, we show how Springs specification language, programming language, software generation system, and operating system kernel are applied to build a flexible manufacturing testbed. The same ingredients have also been used to realize a predictable version of a robot pick and place application used in industry. These applications are good examples of complex real-time systems that require flexibility. The goal of this paper is to demonstrate the integrated nature of the system and the benefits of integration; in particular, the use of reflective information and the value of function and time composition. The lessons learned from these applications and the project as a whole are also presented.

Design and performance of configurable endsystem scheduling mechanisms

This paper describes a scheduling abstraction, called group scheduling, that emphasizes fine grain configurability of system scheduling semantics. The group scheduling approach described and evaluated in this paper provides an extremely flexible framework within which a wide range of scheduling semantics can be expressed, including familiar priority and deadline based algorithms. The paper describes both OS and middleware based implementations of the framework, and shows through evaluation that they can produce the same behavior for a nontrivial set of application computations. We also show that the framework can support application-specific scheduling constraints such as progress, to improve performance of applications whose scheduling semantics do not match those of traditional scheduling algorithms.

The spring scheduling coprocessor: a scheduling accelerator

The spring scheduling coprocessor is a novel very large scale integration (VLSI) accelerator for multiprocessor real-time systems. The coprocessor can be used for static as well as online scheduling. Many different policies and their combinations can be used (e.g., earliest deadline first, highest value first, or resource-oriented policies such as earliest available time first). In this paper, we describe a coprocessor architecture, a CMOS implementation, an implementation of the host/coprocessor interface and a study of the overall performance improvement. We show that the current VLSI chip speeds up the main portion of the scheduling operation by over three orders of magnitude. We also present an overall system improvement analysis by accounting for the operating system overheads and identify the next set of bottlenecks to improve. The scheduling coprocessor includes several novel VLSI features. It is implemented as a parallel architecture for scheduling that is parameterized for different numbers of tasks, numbers of resources, and internal wordlengths. The architecture was implemented using a single-phase clocking style in several novel ways. The 328 000 transistor custom 2-/spl mu/m VLSI accelerator running with a 100-MHz clock, combined with careful hardware/software co-design results in a considerable performance improvement, thus removing a major bottleneck in real-time systems.

ORB middleware evolution for networked embedded systems

Standards-based COTS (common-off-the-shelf) middleware has been shown to be effective in meeting a range of functional and QoS (quality of service) requirements for distributed real-time and embedded (DRE) systems. Each standard makes limiting assumptions, often implicit, about the fundamental set of system capabilities and constraints typical of the domain to which the standard applies. When the characteristics of a particular class of systems violates a standards assumptions, it may be appropriate to modify or extent the standard and its conforming implementations to better match the actual characteristics of that class of systems while still exploiting the capabilities of the standard. In this paper, we argue that key assumptions upon which even the more advanced middleware standards are based, e.g., Real-Time CORBA (RT-CORBA), are violated by an important class of DRE systems characterized by the following properties: (1) highly connected networks of (2) numerous memory-constrained endsystems, with (3) stringent timeliness requirements, and (4) support for adaptive reconfiguration of computation and communication elements and their associated timeliness requirements. We describe our recent work on nORB, a small footprint ORB middleware framework for the Boeing Open Experimental Platform (OEP) under the DARPA Nest program, to meet this entire set of requirements by adapting, unifying, and extending patterns and techniques from earlier related research on COTS middleware frameworks, such as UBI-core, ACE, Kokyu, and TAO.

Group scheduling in systems software

Summary form only given. Previous system scheduling approaches have focused primarily on system-level abstractions for scheduling decision functions and the mechanisms used to implement them. We introduce a new abstraction called group scheduling that focuses primarily on the progress of application-level computations and on organizing system-level scheduling abstractions to ensure that progress. We make three contributions to system scheduling research. First, it defines a model for group scheduling that augments and complements hierarchical scheduling models. Second, it describes how a computations progress semantics can be mapped to scheduling mechanisms at the operating system and middleware levels. Third, it presents preliminary empirical studies of the performance of group scheduling in a realistic system environment.

Integrated CORBA scheduling and resource management for distributed real-time embedded systems

Integration of middleware scheduling and resource management services enables open distributed real-time embedded (DRE) applications to meet end-to-end quality of service (QoS) requirements in highly variable operating environments. This paper describes our research on integrating CORBA scheduling and resource management services, and presents experiments we conducted to validate and quantify the benefits of this integration. Our experimental results show that integrating distributed scheduling and resource management in middleware for open DRE systems can offer significant improvements in predictability. Specifically, integrating our stand-alone resource management service with a previously unmanaged experimental baseline application reduced the ratio of missed deadlines from 26% to 10%, and the same application performed even better under the control of integrated scheduling and resource management services, with a missed deadline ratio of only 1%.