Dragana Prokin

Low Hardware Complexity Pipelined Rank Filter

The major benefit of a disclosed low-hardware-complexity pipelined rank filter is reduction in hardware complexity and increase in processing speed, due to identical pipelined stages and the absence of mask bits. Field-programmable-gate-array realization of this filter significantly reduces the number of used logic elements and registers, in comparison with the best prior art methods, and, at the same time, increases the maximum operating frequency. One rank-sample result is available at the output on each clock cycle, thus enabling real-time nonlinear image processing.

Hardware realization of inverse subband transformer with minimum used resources

State-of-the-art inverse subband transformer implementations employ significant amount of memory resources for the realization of synchronization memory banks between different levels of the composition. This paper presents a hardware realization of inverse subband transformer without synchronization memory banks between different levels of the composition. Such realization achieves significant savings in both memory and logic resources. The proposed realization also provides significant savings in time resources due to a minimum delay which inverse subband transformer introduces into an image decompression system.State-of-the-art direct subband transformer implementations employ significant amount of memory resources for the realization of synchronization memory banks between different levels of the decomposition. This paper presents a hardware realization of direct subband transformer without synchronization memory banks between different levels of the decomposition. Such realization achieves significant savings in both memory and logic resources. The proposed realization also provides significant savings in time resources due to a minimum delay which direct subband transformer introduces into an image compression system.

An image codec with minimum memory size

State-of-the-art image compression methods with high compression ratio are time consuming and require complex processors and large memory with huge bus bandwidth. This paper presents novel method for significantly minimizing required memory size and increasing the encoding and decoding speed. This solution utilizes order(s) of magnitude less system resources (processor complexity, memory size, consumed power and bus bandwidth) versus state-of-the-art methods.

High-Performance 1-D and 2-D Inverse DWT 5/3 Filter Architectures for Efficient Hardware Implementation

This paper presents high-performance and memory-efficient hardware architectures for one-dimensional (1-D) and two-dimensional (2-D) inverse discrete wavelet transform (DWT) 5/3 filters. The proposed 1-D filter architecture requires 33% less memory resources and 17% less logic resources than the best state-of-the-art solutions. The proposed 1-D filter architecture has 100% hardware utilization, which is defined as the ratio of the actual computation time to the total processing time, both expressed in numbers of clock cycles. It allows a 7% higher operational frequency and simultaneously has the lowest total power dissipation in comparison with the best state-of-the-art solutions. The proposed 2-D inverse DWT 5/3 architecture, based on the proposed 1-D inverse DWT filter design, provides medium total computing time and output latency, but outperforms the best state-of-the-art solutions for at least 20% in terms of required memory capacity.

GPRS terminals for reading fiscal registers

Data security in non-fiscal cash registers and non-fiscal printers is minimal. However, data security in fiscal cash registers and fiscal printers is also not satisfactory. This paper describes turnover control devices based on GPRS terminals for sending data from fiscal electronic cash registers and fiscal printers to the server of Tax Administration in order to prevent tax evasion, diversion of original goods from the distribution system and infiltration of counterfeited or original goods into the distribution system without payment of customs, tax and excise duties. The comparison with ordinary fiscal cash registers and non-fiscal cash registers is also provided.

Efficient one-dimensional forward and inverse discrete wavelet transformers

Abstract This paper describes the efficient one-dimensional forward and inverse discrete wavelet transformers with 5/3 filter. This design reuses the same registers for both low-pass and high-pass filtering in different time slots. It utilizes 33% less registers, 17% less logic elements, has 7% higher maximum operating frequency and 2% lower total power dissipation than state-of-the-art filters.

Efficient inverse discrete wavelet transformer

This paper describes the efficient one-dimensional inverse discrete wavelet transformer with 5/3 filter. The described design makes use of the same registers for both low-pass and high-pass filtering in different time slots. The design utilizes 33% less registers, 17% less logic elements, has 7% higher maximum operating frequency and 2% lower total power dissipation than state-of-the-art filters.

Efficient forward discrete wavelet transformer

This paper describes the efficient one-dimensional forward discrete wavelet transformer with 5/3 filter. This design reuses the same registers for both low-pass and high-pass filtering in different time slots. It utilizes 33% less registers, 17% less logic elements, has 7% higher maximum operating frequency and 2% lower total power dissipation than state-of-the-art filters.

Improved fiscal devices without additional services

This paper discloses improved existing or new fiscal cash registers and fiscal printers with improved existing or new internal or external communication devices without additional services, sending encrypted tax related information to a tax administration server.

Novel one-dimensional and two-dimensional forward discrete wavelet transform 5/3 filter architectures for efficient hardware implementation

We implemented a more efficient circuit for one-dimensional (1-D) forward discrete wavelet transform (DWT) 5/3 filter. Our design utilizes processing and memory resources that are wasted in some other state-of-the-art solutions and is at least 33% simpler in terms of used registers, is 17% simpler in terms of used logic elements, has 7% higher maximum operating frequency and has 2% lower total power dissipation than previously published designs. The advantages of our design are achieved by a novel non-stationary filter topology which reuses the same registers for generating both low-pass and high-pass output coefficients, in different time slots, due to feed-forward and feedback paths. Our design is suitable for image compression systems which use 5/3 filter, e.g., JPEG 2000. We also proposed two-dimensional (2-D) DWT 5/3 architecture which uses implemented 1-D DWT filter design. The proposed 2-D DWT architecture outperforms all previously published architectures in terms of required memory capacity, which is at least 20% lower than memory capacity in any other reported solution.