Duan Zongtao

ADV212-based High Resolution Still Image Compression System Design

ADV212 is a SOC which is to implement JPEG2000 encoding and decoding. An embedded RISC processor, a dedicated wavelet transform engine, three entropy codec and on-chip memory system are integrated in ADV212. It provides a complete JPEG2000 compression and decompression solution for real-time application of standard or high resolution video or still image. The ADV212 implements the function described in the JPEG2000 Standard Part I except the ROI. Two chips of ADV212 are used to perform lossy and lossless compression of high resolution aero image. The system architecture is mainly discussed in the paper and also the software and hardware design method to use ADV212 to compress still image. The experimental results show that the system could implement real-time compression of high resolution aero image.

An Overview of Data Bandwidth Hierarchy for an Embedded Stream Processor

The overall speed of computation is determined not just by the speed of the processor, but also by the ability of the memory system to feed data to it. Imagine is a novel image processor which is constructed by a research group of Stanford University. A brand new data bandwidth hierarchy of this processor is introduced in this article. This new data bandwidth hierarchy is constructed by local register file(LRF), stream register file(SRF) and main memory. LRF is used by the ALU clusters. SRF looks like cache in traditional processor. But SRF is a specific unit in stream processor. SRF is used as a stream load/store unit in stream processor. Using this kind of data bandwidth hierarchy the image processing speed is improved greatly.