Duc D. Nguyen

Insight into the multicomponent nature of negative bias temperature instability

A novel measurement technique is used to extract two physically distinct “permanent” (long lived on our experimental time scale, ≤12 000 s) and one recoverable charge components of the negative bias temperature instability in p-channel metal–oxide–semiconductor field effect transistors under inversion and n-channel devices under accumulation. The results suggest that the permanent components are present in both cases, while there is little, if any, recoverable charge present in the case of the n-channel device. A physical explanation is provided involving the band energy diagram to explain these observations.

Transient measurements of carrier relaxation time and density in the P3HT:PCBM organic photovoltaic cell

The authors have used transient photovoltage measurements to evaluate carrier relaxation times (τ) in P3HT:PCBM based photocells over a wide range of open circuit voltages. Satisfactory agreement is found with data obtained by low frequency impedance measurements. The authors find the differential capacitance measurements yield data consistent with the theoretical value expected based on Langevin recombination. The Langevin coefficient is three orders of magnitude smaller than the theoretical one. For the low light levels, the relaxation time variation is determined by the RC time constant behavior of the photodiode.

On the nature of “permanent” degradation in NBTI

This paper reports new high temperature measurements of Negative Bias Temperature Instability induced interface states in both NMOS and PMOS devices. Evidence of annealing of the interface states, previously thought to be “permanent”, is presented for measurements including a methodology which allows the direct measurement of the time dependent growth/recovery of the interface state component.

Tunneling discharge of positive trapped oxide charge in p-channel field effect transistors

Negative bias temperature instability has been studied in 130 nm and 90 nm channel length, SiO2 gate insulator field effect transistors at room temperature. Pulsed voltage stressing and subsequent recovery using times starting in the tens of microsecond regime were employed together with a single point data acquisition time ∼4 μs. Threshold voltage shifts were characteristic of oxide charge trapping as opposed to interface state generation. Recovery of the threshold voltage was modeled assuming quantum mechanical tunneling of trapped charges from the dielectric to the Si substrate.

Ionizing radiation induced parametric variations in P3HT:PCBM organic photovoltaic cells

The authors have examined ionizing radiation effects in the organic photovoltaic material poly(3-hexylthiophene):([6, 6]-phenyl C61 butyric acid methyl ester) for total accumulated doses up to 300 krad(SiO2). The authors find that the open circuit voltage varies with the accumulation of irradiation; however, the other parameters such as relaxation time, short circuit current, and charge carrier density remain to first order constant. This behavior is inconsistent with observations on preirradiation devices in which all depend directly on the open circuit voltage.

Measurement and modeling of duty-cycle effects due to NBTI

One of the most important requirements for modeling of the long-term effects of negative bias temperature instability (NBTI) on device/circuit response is an understanding of how to include the effect of duty cycle on the threshold voltage shift. Since NBTI is known to be comprised of both permanent and recoverable components, a measurement protocol must be established enabling separation of these components and then their recombination to predict the shift for different duty cycles. In the work reported here, we have endeavored to address these issues by combining pulsed and pseudo-DC stressing/relaxation methods.

Effect of radiation induced charging on gate-all-around NMOS devices

The need for more reliable and radiation hard complementary metal–oxide–semiconductor compatible devices coupled with an ever increasing shrinkage of device dimensions has led naturally to interest in metal-oxide semiconductor field-effect transistors having nontraditional geometries. One such geometry is the gate-all-around transistor, which has been suggested to be less sensitive than its planar counterpart to the effect of charge build-up at the semiconductor–insulator interface such as that induced by irradiation. In order to explore the radiation hardness of such a structure, the effect of radiation on gate-all-around n-type metal–oxide–semiconductor devices was investigated by computing the effect of charging on the threshold voltage of the device. The radiation sensitivity in ideal structures is explored, and the greater radiation sensitivity found experimentally in some devices is explained.

Comparison of duty-cycle effects at room temperature in SiON and HfO 2 gate PMOS FETS

The existence of multiple, physically distinct components of Negative Bias Temperature Instability requires a measurement methodology which allows the extraction of each component independently. In this paper we present results obtained at room temperature, which minimizes both the interface state and switching trap components, allowing us to explore the trapping of holes at preexisting defects in the oxide. This is done for both SiON and HfO2/SiO2 oxide stacks of similar total thickness. Results are presented for both pseudo-DC and pulse stressing including the dependence of the pulse measurements on duty cycle. A two trap model using the Tewksbury formalism is proposed to predict the results.

Direct evidence for interface state annealing in the negative bias temperature instability response

Using a rapid data acquisition methodology, the authors examine the time dependent recovery of the “permanent” component of charge build-up due to the negative bias temperature instability in Si based p-channel field effect transistors in inversion and n-channel devices in accumulation. The authors find clear evidence for recovery of the charge associated with interface states for elevated temperatures (≥150 °C) and for extended times (trecover ∼ 20 000 s). Recovery appears to begin at shorter times for p-channel devices than for n-channel. An explanation is advanced both for the mechanism of interface state annealing and for the difference observed between p and n channel devices.

Comparison of NTBI and irradiation induced interface states

The generation of interface states created by depassivating dangling bonds at the interface between the gate dielectric and silicon substrate is important for both the growth of Negative Bias Temperature Instability threshold voltage shift in MOSFETs and the radiation sensitivity of the devices. In this paper we present results comparing the generation of interface states for both processes and their possible annealing at high temperatures.