Duo Sheng

An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications

In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with conventional approaches. Besides, the proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Measurement results show that power consumption of the proposed DCO can be improved to 140 muW (@200 MHz) with 1.47-ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.

An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications

In this paper, we propose a very high-resolution all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by hardware description language (HDL). The proposed ADPLL uses a novel digitally controlled oscillator (DCO) to achieve 1.06ps resolution and the proposed DCO can extend the controllable range easily. The dead zone of the proposed phase/frequency detector (PFD) is 5ps. The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP) block, making it very suitable for system-on-chip (SoC) and system-level applications

A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications

In this paper, a novel portable and all-digital spread spectrum clock generator (ADSSCG) suitable for system-on-chip (SoC) applications with low-power consumption is presented. The proposed ADSSCG can provide flexible spreading ratios by the proposed rescheduling division triangular modulation (RDTM). Thus it can provide different EMI attenuation performance for various system applications. Furthermore, the proposed ADSSCG employs a low-power digitally controlled oscillator (DCO) to save overall power consumption significantly. Measurement results show that power consumption of the proposed ADSSCG is 1.2 mW (@54 MHz), and it provides 9.5 dB EMI reductions with 1% spreading ratio. Besides, the proposed ADSSCG has very small chip area as compared with conventional SSCGs which often required large on-chip loop filter capacitors. In addition, the proposed ADSSCG is implemented only with standard cells, making it easily portable to different processes and very suitable for SoC applications.

High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

In high-speed data transmission applications, such as double data rate memory and double sampling analog-to-digital converter, the positive and negative edges of the system clock are utilized for data sampling. Thus, these systems require an exact 50% duty cycle of the system clock. In this paper, two wide-range all-digital duty-cycle correctors (ADDCCs) with output clock phase alignment are presented. The proposed phase-alignment ADDCC (PA-ADDCC) not only achieves the desired output/input phase alignment, but also maintains the output duty cycle at 50% with a short locking time. In addition, the proposed high-resolution ADDCC (HR-ADDCC) without a half-cycle delay line can improve the delay resolution and mitigate the delay mismatch problem in a nanometer CMOS process. Experimental results show that the frequency range of the proposed ADDCCs is 263-1020 MHz for the PA-ADDCC and 200-1066 MHz for the HR-ADDCC with a DCC resolution of 3.5 and 1.75 ps, respectively. In addition, the proposed PA-ADDCC and HR-ADDCC are implemented in an all-digital manner to reduce circuit complexity and leakage power in advanced process technologies and, thus, are very suitable for system-on-chip applications.

A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications

This paper proposed a fast-lock-in all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by hardware description language (HDL). The proposed ADPLL uses a novel 2-level flash time-to-digital converter (TDC) to lock in within 2 reference clock cycles. The novel digitally controlled oscillator (DCO) achieves high-resolution with 0.93ps resolution and can extend the controllable range easily. In addition to high-resolution, the power consumption of the proposed DCO can be lowered as 110muW(@200MHz). The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP), making it very suitable for system-on-chip (SoC) applications as well as system-level power management

A high-performance wear-leveling algorithm for flash memory system

In this paper, a low-complexity high-performance wearleveling algorithm which named sequential garbage collection (SGC) for flash memory system design is presented. The proposed SGC outperforms existing designs in terms of wear evenness and low design complexity. The lifetime of the flash memory can be greatly lengthened by the proposed SGC. The proposed SGC doesn’t require any tuning threshold parameter, and thus it can be applied to various systems without prior knowledge of the system environment for threshold tuning. Simulation results show that the maximum block erase count and standard deviation of the block erase count compared to the greedy algorithm are decreased by up to 75% and 94%, respectively.

A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator

In this brief, a low-cost low-power all-digital spread-spectrum clock generator (ADSSCG) is presented. The proposed ADSSCG can provide an accurate programmable spreading ratio with process, voltage, and temperature variations. To maintain the frequency stability while performing triangular modulation, the fast-relocked mechanism is proposed. The proposed fast-relocked ADSSCG is implemented in a standard performance 90-nm CMOS process, and the active area is 200 μm × 200 μm. The experimental results show that the electromagnetic interference reduction is 14.61 dB with a 0.5% spreading ratio and 19.69 dB with a 2% spreading ratio at 270 MHz. The power consumption is 443 μW at 270 MHz with a 1.0 V power supply.

Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications

A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90° phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3° at 400MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides the suitable phase shift of control signals for DDR interface where precise control is the key to reliable high-performance operation. Besides, the cell-based implementation makes it easy to target a variety of technologies as a soft silicon intellectual property (IP).

A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications

In this paper, a monotonic and low-power digitally controlled oscillator (DCO) with cell-based design for System-On-Chip (SoC) applications is presented. The proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Besides, based on the proposed two-level controlled interpolation structure, the proposed DCO can provide monotonic delay with low power consumption and low circuit complexity as compared with conventional approaches. Simulation results show that power consumption of the proposed DCO can be improved to 0.337mW (@1118MHz) with 0.82ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.

An all digital spread spectrum clock generator with programmable spread ratio for SoC applications

In this paper, a programmable all-digital spread spectrum clock generator (ADSSCG) suitable for system-on-chip (SoC) applications with ultra-low-power capability is presented. Based on the timing constraint of system, the programmable ADSSCG can provide the suitable frequency spread ratio to obtain the optimal combination of timing deviation and EMI reduction for system applications. Besides, the proposed ADSSCG employs an ultra-low-power digitally controlled oscillator (DCO) to save overall power consumption to 560 muW (@400 MHz) and the peak EMI power reduction is large than 25 dB. In addition, the proposed ADSSCG can be implemented only with standard cells; as a result, the area can be saved without any passive component, and making it easily portable to different processes and very suitable for SoC applications.