Durgesh Srivastava

The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series

The 16-way set associative, single-ported 16-MB cache for the Dual-Core Intel Xeon Processor 7100 Series uses a 0.624 mum2 cell in a 65-nm 8-metal technology. Low power techniques are implemented in the L3 cache to minimize both leakage and dynamic power. Sleep transistors are used in the SRAM array and peripherals, reducing the cache leakage by more than 2X. Only 0.8% of the cache is powered up for a cache access. Dynamic cache line disable (Intel Cache Safe Technology) with a history buffer protects the cache from latent defects and infant mortality failures

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

An × 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.

The 65nm 16MB On-Die L3 Cache for a Dual Core Multi-Threaded Xeon/sup ~/ Processor

The 16-way set associative, single-ported 16MB cache for the dual-core Xeonreg processor uses a 0.624mum2 cell in a 65nm 8-metal technology. Only 0.8% of the cache is powered up for an access. Sleep transistors are used in the SRAM array and peripherals. Dynamic Pellston with a history buffer protects the cache from latent defects and infant mortality failures

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver

Embedded PC applications are growing, driven by their cost, performance and software compatibility. The SoC described in this work is a unique device designed for rapid integration and customization for specific market segments. A rich multi-source IP eco-system consisting of standardized interfaces, modular and configurable building blocks, enables automation and fast execution to deliver a broad range of targeted solutions. Integrating high-performance digital circuits with analog and RF circuits on a leading edge process enables our SoC architecture to increase the level of integration, performance and reduce the cost of the platform. WiFi has remained an external PC component due to the challenges of managing system noise from the digital circuits. This paper presents an integrated standard x86 OS compliant, dual-core ATOM® processor-based SoC, including the RF WiFi to drive down platform cost. Key enabling features are: (a) a 32nm RF process with HV transistors and RF passives; (b) an on-chip interconnect fabric for modularity; (c) a clock generator with SSC to reduce substrate noise injection and EMI; (d) voltage regulators for power management and rail reduction; (e) an 802.11b/g RF WiFi transceiver with integrated LNA, PA, T/R switch and BIST/calibration engine.