E. Barrera

PXI-based architecture for real time data acquisition and distributed dynamical data processing

This paper describes an architecture model for data acquisition systems based on compact PCI platforms. The aim is to increase real time data processing capabilities in experimental environments such as nuclear fusion devices (e.g. ITER). The model has these features: a) real time data acquisition: the system has been provided with real time capabilities, developing specific data acquisition kernel modules under Linux and RTAI, using COMEDI project drivers; b) multiprocessor PXI (PCI extension for instrumentation) architecture: the model makes possible to add one or more processing cards (in non-system slots) to each standard PXI chassis. Several real time software modules have been developed to allow the communication between the PXI controller and the processing cards. This way the system performance is not restricted to the PXI controllers own performance. This model provides scalability to the system, adding or removing processing cards; c) real time acquired data distribution: with this model it is possible to define how to distribute, in real time, the data from all acquired signals in the system among the processing cards and the PXI controller; and d) dynamical data processing: a software platform has been developed to allow users managing dynamically their own data processing algorithms in the system. This means that users can start, stop, modify, and replace their data processing algorithms without disrupting neither the data acquisition process nor the rest of the data processing algorithms

Distributed real time data processing architecture for the TJ-II data acquisition system

This article describes the performance of a new model of architecture that has been developed for the TJ-II data acquisition system in order to increase its real time data processing capabilities. The current model consists of several compact PCI extension for instrumentation (PXI) standard chassis, each one with various digitizers. In this architecture, the data processing capability is restricted to the PXI controller’s own performance. The controller must share its CPU resources between the data processing and the data acquisition tasks. In the new model, distributed data processing architecture has been developed. The solution adds one or more processing cards to each PXI chassis. This way it is possible to plan how to distribute the data processing of all acquired signals among the processing cards and the available resources of the PXI controller. This model allows scalability of the system. More or less processing cards can be added based on the requirements of the system. The processing algorithms...

Ultrasonic wave-based structural health monitoring embedded instrument

Piezoelectric sensors and actuators are the bridge between electronic and mechanical systems in structures. This type of sensor is a key element in the integrity monitoring of aeronautic structures, bridges, pressure vessels, wind turbine blades, and gas pipelines. In this paper, an all-in-one system for Structural Health Monitoring (SHM) based on ultrasonic waves is presented, called Phased Array Monitoring for Enhanced Life Assessment. This integrated instrument is able to generate excitation signals that are sent through piezoelectric actuators, acquire the received signals in the piezoelectric sensors, and carry out signal processing to check the health of structures. To accomplish this task, the instrument uses a piezoelectric phased-array transducer that performs the actuation and sensing of the signals. The flexibility and strength of the instrument allow the user to develop and implement a substantial part of the SHM technique using Lamb waves. The entire system is controlled using configuration software and has been validated through functional, electrical loading, mechanical loading, and thermal loading resistance tests.

Multi-tier approach for data acquisition programming in the TJ-II remote participation system

Programming software to setup acquisition channels during device operation has been developed for the TJ-II remote participation system. The software follows a three-tier model. A first tier (client tier) groups client software containing only user interface code. A second tier (middle tier) includes code for authorization, authentication, and query processing. A third tier (data tier) consists of a relational database server for managing configurations. Multi-platform characteristics are provided by web browsers (client tier) and web servers (middle tier). This architecture avoids that data acquisition system controllers provide access control, database support, or graphic user interface resources. Therefore, computation capabilities of these systems can mainly be devoted to data handling. LabView (from National Instruments) has been used as programming language in the acquisition systems. This design allows a very transparent management of signals, independently on hardware modules and systems.

Design of the TJ-II remote participation system

The TJ-II remote participation design has focused initially on providing remote access to elements that depend exclusively on characteristics of the TJ-II environment: data acquisition, data access, and diagnostics control systems. Aspects related to advanced display tools, audio information from the control room or videoconference sessions can be addressed, at least in a first step, by using standard solutions. Remote access will be accomplished through http servers and web browsers as they are standard elements available on all platforms. Access security rests on a validation scheme in which users are identified through a username and password, these data being transferred in a secure way by using a secure socket layer (SSL). After username and password validation, the security system assigns a session ticket to the user, in which the user profile (access authorization list) is encoded. User profiles determine several access levels to the system. Such levels delimit the authorizations for accessing different services according to the allowed degree of interaction of remote users with the TJ-II environment. The ticket will be sent in every user query, in order to test user permission for the requested action. Services can be classified into five groups: Measurement channel setup, read/write access to the TJ-II databases (raw data, analyzed data, elaborated data, and relational databases), diagnostic control system monitoring/programming, advanced data acquisition system configuration and, finally, reading/writing information on TJ-II operation logbook. The TJ-II remote participation system is strongly coupled with the local data acquisition system.

Implementation of ITER Fast Plant Interlock System Using FPGAs With CompactRIO

Interlocks are the instrumented functions of ITER that protect the machine against failures of the plant system components or incorrect machine operation. Regarding instrumentation and control, the interlock control system (ICS) ensures that no failure of the conventional ITER controls can lead to a serious damage of the machine integrity or availability. The ICS is in charge of the supervision and control of all the ITER components involved in the instrumented protection of the tokamak and its auxiliary systems. It is constituted by the central interlock system (CIS), different plant interlock systems (PISs), and its networks. The ICS does not include the sensors and actuators of the plant systems, but it is in charge of their control. The ITER interlock system shall be designed, built, and operated according to the highest quality standards. The international standard IEC-61508 has been chosen as the reference. In both CIS and PIS cases, two main architectures are used: 1) a slow architecture, for those functions with response time requirements slower than 100 ms (300 ms for central interlock functions), based on programmable logic controller technologies and 2) a fast architecture, based on field programmable gate array (FPGA) technologies, for the functions with faster requirement times. The proposed design for fast PIS is based on the use of reconfigurable input/output (RIO) technology from National Instruments (NI CompactRIO platform). In order to provide a high integrity solution, failure modes, effects, and diagnostic analysis (FMEDA) has been conducted to analyze the component behavior. According to the output of the FMEDA, a set of diagnostics has been defined and additional redundancy was added to the architecture to improve the integrity figures. The defined configuration has been called the “double-decker solution,” with two chassis running in parallel, communicated between them using a synchronous high-speed serial line, and using redundant modules to implement the input and output measurements/excitations and redundant analog and digital modules to implement the diagnostics of these input/output modules. The integrity figures for the “double-decker” solution are obtained from the classification of the failure rates, obtaining for different configurations a safe failure fraction of 85% and a probability of dangerous failure per hour of less than 1E−07. The FPGA design includes all the hardware to support the data acquisition from the input modules, the implementation of the diagnostic functionalities for analog and digital modules, the voting schema, and the activation/deactivation of digital outputs. The platform includes an external test platform, also based on NI CompactRIO technology, to perform the validation of the system and to register the performance of different interlock functions implemented. The response time obtained for the transistor–transistor logic (TTL) input to TTL output interlock function ranges from 5 to

IRIO technology: Developing applications for advanced DAQ systems using FPGAs

20~\mu \text{s}

Data processing in fusion experiments with remote participation

; for the analog input to TTL output, the response time is in the range of 41–

Image acquisition and GPU processing application using IRIO technology and FlexRIO devices

90~\mu \text{s}

Analog data acquisition and processing FPGA-based solutions integrated in areaDetector using FlexRIO technology

, and for interlock functions using 24-V digital input to 24-V digital output, the time can rise up to