E. Barsotti

Fastbus data acquisition for CDF

Abstract All CDF event data are collected in a multilevel FASTBUS network. At the lowest level of this network, MEP/MX and SSP scanners read and buffer data from RABBIT and FASTBUS front end systems. Operation of these front end scanners is coordinated by the Trigger Supervisor module which initiates parallel readout after receiving Level 1 and Level 2 triggers. Dataflow from scanners to consumer processes on host VAX computers is supervised by the Buffer Manager which directs an Event Builder to collect and format data from a set of scanner modules. This system is designed to allow partitioning into semi-independent sections for parallel development and calibration studies.

Results from a data acquisition system prototype project using a switch-based event builder

A prototype of a high-bandwidth parallel event builder has been designed and tested. The architecture is based on a simple switching network and is adaptable to a wide variety of data acquisition systems. An eight-channel system with a peak throughput of 160 Mbytes/s has been implemented. It is modularly expandable to 64 channels (over 1 Gbyte/s). The prototype uses a number of relatively recent commercial technologies, including very-high-speed fiber-optic data links, high integration crossbar switches, and embedded RISC processors. It is based on an open architecture which permits the installation of new technologies with little redesign effort.<<ETX>>

Test stand for the Silicon Vertex Detector of the Collider Detector Facility

A test stand for the next generation of the Silicon Vertex Detector (SVX-II) of the Collider Detector Facility (CDF) at Fermilab has been developed. It is capable of performing cosmic ray, beam, and laser pulsing tests on silicon strip detectors using the new generation of SVX chips. The test stand is composed of a SGI workstation, a VME CPU, the Silicon Test Acquisition and Readout (STAR) board, the Test Fiber Interface Board (TFIB), and the Test Port Card (TPC). The STAR mediates between external stimuli for the different tests and produces appropriate high level commands which are sent to the TFIB. The TFIB, in conjunction with the TPC, translates these commands into the correct logic levels to control the SVX chips. The four modes of operation of the SVX chips are configuration, data acquisition, digitization, and data readout. The data read out from the SVX chips is transferred to the STAR. The STAR can then be accessed by the VME CPU and the SGI workstation for future analyses. The detailed description of this test stand will be given.

Data acquisition and online processing requirements for experimentation at the superconducting super collider

Differences in scale between data acquisition and online processing requirements for detectors at the Superconducting Super Collider and systems for existing large detectors will require new architectures and technological advances in these systems. Emerging technologies will be employed for data transfer, processing, and recording. 9 refs., 3 figs.

FASTBUS standard fiber optic data transfer link

The authors describe a unidirectional/bidirectional fiber-optic data transfer link being specified by the FASTBUS Standards Committee that can be incorporated into FASTBUS as well as other data acquisition systems. The FASTBUS or bidirectional mode allows relatively slow, long-distance communication of the full FASTBUS protocol. The high-speed transfer or unidirectional mode is optimized for pipelined data transfers with minimum handshaking overhead. This link is bus-independent and can be used to transfer data at high speeds between sets of devices each packaged in any bus standard or black-box implementation. Serial protocol flexibility permits the link to be used also as a central link. Simple messages are transmitted over this link to common data flow from front-end equipment to buffer memories or processor farms. The proposed FASTBUS serial line protocol and recommended optical hardware are detailed. An application example using the fiver-optic data link in a FASTBUS data acquisition system is shown. >

FASTBUS Review 1984

The first year of work with the FASTBUS Specification DOE/ER-0189 for modular high speed data acquisition and control systems is reviewed. FASTBUS system components such as crates, power supplies, modules, and diagnostic tools available from research laboratories and industry in North America and Japan are summarized. New developments and future plans for applications and products are highlighted. European progress on FASTBUS and review of software activities are presented in other papers at this Conference. Relevant background information may be found in the FASTBUS status report presented at the 1983 Nuclear Science Symposium.

Status of the Segment Interconnect, Cable Segment Ancillary Logic, and the Cable Segment Hybrid Driver Projects

The FASTBUS Segment Interconnect (SI) provides a communication path between two otherwise independent, asynchronous bus segments. In particular, the Segment Interconnect links a backplane crate segment to a cable segment. All standard FASTBUS address and data transactions can be passed through the SI or any number of SIs and segments in a path. Thus systems of arbitrary connection complexity can be formed, allowing simultaneous independent processing, yet still permitting devices associated with one segment to be accessed from others. The model S1 Segment Interconnect and the Cable Segment Ancillary Logic covered in this report comply with all the mandatory features stated in the FASTBUS specification document DOE/ER-0189. A block diagram of the SI is shown.

Testing of the HP G-Link chip set for an event builder application

The Hewlett Packard HDMP-1000 G-Link transmitter and receiver chip set was tested for an event builder application. The re-lock time of the serial link when a data path is changed is less than 30 /spl mu/s provided fill frames are transmitted. With a 1 kHz data path switching rate, this results in less than a 3% data rate inefficiency due to re-synchronization, which makes the HP G-Link chip set effective for use in a large event builder for a hadron collider experiment. >

A comparison of high-speed data links, their commercial support and ongoing R&D activities

The authors describe high-speed communication links and protocols of interest for high-energy physics data acquisition systems. The protocols covered are High Performance Parallel Interface (HIPPI), Serial HIPPI, Fibre Channel (FC), and Scalable Coherent Interface (SCI). The initial work required to implement an SDC (Solenoidal Detector Collaboration)-like data acquisition system is also described.<<ETX>>