E. Heine

Very low power, high voltage base for a Photo Multiplier Tube for the KM3NeT deep sea neutrino telescope

The described system is developed in the framework of a deep-sea submerged Very Large Volume neutrino Telescope where photons are detected by a large number of Photo Multiplier Tubes. These PMTs are placed in optical modules (OM). A basic Cockcroft-Walton (CW) voltage multiplier circuit design is used to generate multiple voltages to drive the dynodes of the photomultiplier tube. To achieve a long lifetime and a high reliability the dissipation in the OM must be kept to the minimum. The design is also constrained by size restrictions, load current, voltage range, and the maximum allowable ripple in the output voltage. A surface mount PMT-base PCB prototype is designed and successfully tested. The system draws less than 1.5 mA of supply current at a voltage of 3.3 V with outputs up to -1400 Vdc cathode voltage, a factor 10 less than the commercially available state of the art.

A front end ASIC for the readout of the PMT in the KM3NeT detector

In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I2C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).