E. Kubalek

Voltage contrast in integrated circuits with 100 nm spatial resolution by scanning force microscopy

A new contactless device internal test technique is introduced based on a scanning force microscope enabling dynamic voltage contrast within passivated integrated circuits. A spatial resolution below 500 nm and voltage resolution down to voltages of 0.2 V amplitude are achieved. For the first time static voltage contrast obtained with the scanning force microscope is shown on passivated integrated circuits. Potential and limits of this test technique are discussed.

Evaluation of three-dimensional micromagnetic stray fields by means of electron-beam tomography

A novel method is described allowing quantitative evaluation of micromagnetic stray fields with submicron resolution. The method is three-dimensional in that it delivers the magnetic field vector at all points of a three-dimensional space about the specimen. The measuring principle is the deflection of an electron beam due to the Lorentz force. For a plane bundle of electron beams passing the surface of the measuring object the deflections of the beam trajectories are measured. This measurement is repeated several times while the object is beeing rotated a small angle about an axis normal to the plane spanned by the electron beams. From the data thus obtained the field is computed by means of a newly developed tomographic reconstruction procedure. Because of the inherent properties of a magnetic stray field this reconstruction procedure turns out to be far less costly then expected in view of ordinary tomography. Computer simulations and first experimental tests prove the applicability of the method.

Design for e-beam testability - A demand for e-beam testing of future device generations ?

Based on the trends in development of integrated circuits (IC) until the year 2000 it is shown that, presuming the present capability of electron beam test systems, in future an electron beam test (EBT) will not be practicable anymore. This is mainly due to long measurement times, large measurement errors at passivated IC and the restricted test access. Of course, the performance of EBT may be improved significantly by improved equipment in order to meet the requirements given by the IC development as will be pointed out in this work. However, the physical limitations can already be foreseen. Therefore alternatively to the improvements of equipment a design for e-beam testability (DFEBT) has to be realized. Measures for a DFEBT will be discussed.

Scanning-force-microscope test system for device internal test with high spatial and temporal resolution

Abstract A new device internal test technique is introduced based on a scanning force microscope enabling the electrical characterization of integrated circuits with both high spatial and temporal resolution. Device internal electrical signals are measured time resolved up to 15 GHz and on device structures down to 1 μm.

Two-dimensional direct electra-optic field mapping in a monolithic integrated GaAs amplifier

For the first time experimental results of two-dimensional electric field mapping within a GaAs-MMIC using the direct electro-optic probing technique are presented. As an example, maps of different sections of a coplanar 1-12 GHz travelling-wave amplifier such as a thin film resistor, a MESFET, the drain transmlssion line, and an air-bridge are displayed showing characteristic field distributions in a MMIC amplifier at different driving frequencies. Evaluating the results, signal levels at internal points of the circuit can be studied providing quantitative informations about circuit-internal transmission characteristics such as attenuation or amplification of the microwave signal.

Two-dimensional field mapping in MMIC-substrates by electro-optic sampling technique

A system for two-dimensional field mapping in MMIC (monolithic microwave integrated circuit) substrates using direct electrooptic sampling is introduced. Measurements up to 8.5 GHz have been made. The main application of the field mapping technique is the analysis of complex MMICs. The proposed test technique is characterized by the fact that, due to the small laser beam, a high spatial resolution and a high temporal resolution (<5 ps) can be reached, allowing testing in a contactless and noninvasive manner. It offers a quick survey of the actual internal field distributions, thus making control of the simulation procedure possible. It is evident that by these means easy failure and function analysis within a MMIC can be achieved, leading to significant reduction of the otherwise time-consuming design/redesign loop.<<ETX>>

Contactless electrical characterization of MMICs by device internal electrical sampling scanning-force-microscopy

For the first time a scanning force microscope based test system is used for device internal electrical characterization of monolithic microwave integrated circuits (MMIC) based on III-V-semiconductor material up to 40 GHz. Measurements on a coplanar waveguide and within a travelling wave amplifier (TWA) demonstrate the capability for a device internal function- and failure analysis of MMICs. The experimental results are completed by network analyzer measurements.<<ETX>>

Electron beam testing of monolithic integrated micro- and millimeterwave circuits

Abstract An electron beam testing system has been developed, consisting of a new type of electron beam blanking system and a specimen holder designed for applying GHz-frequencies to the device under test. First quantitative measurements have been done on a special test structure, showing the influence of the transit-time-effect on quantitative measurements. These experimental results were compared with results obtained by simulations, showing good agreement. Although the electron beam testing system works in a frequency range from 8 to 18 GHz the results show that quantitative measurements are only practical for frequencies below 2.5 GHz, assuming a maximum measurement error of 10%.

Scanning transmission electron microscopy of heterointerfaces grown by metalorganic vapor phase epitaxy (MOVPE)

Abstract In this paper we report on the influence of a superlattice (SL) buffer layer and the growth conditions on AlGaAs/GaAs heterojunction properties such as the interface abruptness and interface roughness. The characterization was performed in a field-emission scanning transmission electron microscope (STEM) and by low temperature photoluminescence (PL). By means of STEM micrographs we find that the abruptness and roughness of quantum wells (QW) with and without SL buffer layer is of equal quality. The dramatically improved PL properties of samples with SL buffer layers show that the impurity density in the active layer is strongly reduced by the SL.

Some aspects concerning design for E-beam testability

Abstract Electron beam testing has become a powerful inspection technique for integrated circuits under operation, since an electron beam can act as a non-loading and non-damaging probe which can easily be adressed to any node of the circuit. A successful application of e-beam testing to integrated circuits of higher complexity, however, necessitates modifications of both test equipment and device layout. Essential developments of the testing set-up include use of bright electron beam guns, improvement of electron energy spectrometers and more sensitive signal processing. Furthermore a hybrid test system connecting a CAD design system equipment for VLSI and an e-beam tester has to be established indispensibly in order to obtain exact and automated probing of these nodes by the electron beam. However, there is also a demand for a modified circuit layout being appropriate to e-beam testing due to the following aspects: • - By theoretical treatment the influence of enlarged surfaces of test points on the achievable test duration has to be quantified. • - Numerical simulations quantitatively demonstrate the importance of circuit internal shielding electrodes in the direct vicinity of the probed node on the minimization of measurement errors caused by cross talk from neighbouring conductor tracks. Such calculations are treated for various parameters, such as device geometry, potential distributions and types of electron energy spectrometers. • - Extending the application of e-beam testing to the analysis of passivated devices by means of the capacitive coupling voltage contrast, this method may be strongly falsified by inhomogenous coupling of the local potential distributions at the metallization-passivation-interface with the passivations surface towards vacuum. Testing of multi-level-interconnection-devices is even more influenced by such falsifications and by this only possible for certain device geometries. From the results reported in this paper design rules can be deduced guaranteeing a sufficient e-beam testability for future integrated circuits.