E. Mandelli

A time-over-threshold machine: the readout integrated circuit for the BABAR Silicon Vertex Tracker

A low-noise, mixed-signal, 128-channel CMOS integrated circuit containing the complete readout electronics for the BABAR Silicon Vertex Tracker has been developed. The outstanding feature of the present implementation is the ability to perform simultaneously low-level signal acquisition, derandomizing data storage, sparsification and data transmission on a single monolithic chip. The signals from the detector strips are amplified, shaped by a CR-RC/sup 2/ filter with digitally selectable peaking time of 100 ns, 200 ns, 300 ns, or 400 ns, and then presented to a time-over-threshold processor to implement a compression type analog-to-digital conversion. The digital information is stored, sparsified and read out through a serial link upon receipt of a command. The digital section operates from a 60 MHz incoming clock. Noise measurements at 200 ns peaking time and 3.5 mW total power dissipation per channel yield an equivalent noise charge of 600 el. rms at 12 pF added source capacitance. The chip measures 5.7 mm/spl times/8.3 mm and contains 330 k transistors. The first full-scale prototype was fabricated in a radiation soft 0.8 /spl mu/m, 3-metal CMOS process. The same circuit is now being fabricated in an analogous radiation hard technology.

Noise limits in a front-end system based on time-over-threshold signal processing

Abstract An analog signal processor based on the Time-over-Threshold (ToT) range compression is employed in the front-end section of the readout chip of the microstrip vertex detector for the BaBar experiment. The paper, after describing the circuit solutions that have been adopted to optimize the ToT operation, focuses on the noise aspects of the ToT processor. Comparisons are made between the signal-to-noise ratio in the linear processor preceding the ToT circuit and that obtained at the output of the entire analog channel including the ToT function.

The analog front-end section of the BaBar silicon vertex tracker readout IC

This paper describes the evolution in the analog section of the vertex detector readout chip for the BaBar experiment. In order to optimize its behaviour, an intermediate chip reproducing the analog part alone was developed and tested. It provided some useful design hints that provided the basis for the final conception of the analog front-end as it is now operational in the complete BaBar chip.

Performance, radiation damage, and future plans of the BABAR silicon vertex tracker

The BABAR silicon vertex tracker (SVT) has been in operation for four years at the PEP-II electron-positron storage ring. During this time the SVT modules have accumulated a radiation dose up to 2 Mrad. We study the degradation in the performance of the SVT due to this accumulated dose which is highly non uniform across the device and also within the individual silicon detectors. To extrapolate the performance of the device to the future we study separately the effect of the irradiation on silicon detectors, front end integrated circuits and on a complete detector module under controlled radiation conditions, using a /sup 60/Co source and a 0.9 GeV e/sup -/ beam. We compare the results to the data from the SVT. In particular we show the dependence of the charge collection efficiency on the radiation dose even when a small stripe of the module is irradiated up to space charge sign inversion. Since the modules that are located in the plane of the beams will suffer significant radiation damage, we will describe our plans for their replacement in 2005 and for the operation of the SVT through the lifetime of the BABAR experiment.

Functional characteristics and radiation tolerance of AToM, the front-end chip of BaBar silicon vertex tracker

The readout chip designed to process the microstrip signals in the BaBar silicon vertex tracker (SVT), after being realized twice in a radsoft technology has been transferred into the final radhard process. So far the circuit has gone through four different radhard submissions, one aiming at providing a preliminary insight into the characteristics of the radhard chip, the other ones constituting pre-production and production runs. Chips from these submissions have undergone a thorough set of tests addressing functional aspects, noise parameters and effects of radiation on signal and noise behavior. The present paper discusses the results of these tests and describes the final version of the circuit which has been proven to successfully meet the experiment requirements.

Status and future plans of the BABAR silicon vertex tracker

Abstract A brief summary of the design goals, description, and performance of the BABAR Silicon Vertex Tracker is given. Results from radiation hardness tests are discussed, which indicate satisfactory operation up to 5 Mrad of accumulated radiation. The local alignment procedure has made significant improvements recently, and four readout sections were recovered during the BABAR shutdown in 2002.

Lessons learned from BaBar silicon vertex tracker, limits, and future perspectives of the detector

The silicon vertex tracker (SVT) of the BaBar experiment at PEP-II is described. This is the crucial device for the measurement of the B meson decay vertices to extract charge-conjugation parity (CP) asymmetries. It consists of five layers of double-sided ac-coupled silicon strip detectors, read out by a full-custom integrated circuit, capable of simultaneous acquisition, digitization, and transmission of data. It represents the core of the BaBar tracking system, providing position measurements with a precision of 10 /spl mu/m (inner layers) and 30 /spl mu/m (outer layers). The relevant performances of the SVT are presented, and the experience acquired during the construction, installation, and the first five years of data-taking is described. Innovative solutions are highlighted, like the sophisticated alignment procedure, imposed by the design of the silicon tracker, integrated in the beamline elements and mechanically separated from the other parts of BaBar. The harshness of the background conditions in the interaction region required several studies on the radiation damage of the sensors and the front-end chips, whose results are presented. Over the next five years the luminosity is predicted to increase by a factor three, leading to radiation and occupancy levels significantly exceeding the detector design. Extrapolation of future radiation doses and occupancies is shown together with the expected detector performance and lifetime. Upgrade scenarios to deal with the increased luminosity and backgrounds are discussed.

Radiation hardness characterisation of the front-end chip for the BaBar silicon vertex tracker

Abstract This paper presents the experimental results of radiation hardness studies of the vertex detector readout chip for the BaBar experiment. The chip was fabricated in a rad-hard CMOS technology. It was irradiated in several steps by 60Co γ-rays to a total dose of 2.4 Mrad. After irradiation, the chip is fully functional, with small parameter degradation. This analysis demonstrates that the chip can operate throughout the lifetime of the detector, always meeting the primary performance criteria.

Design hints for best noise and signal behaviour in DMILL amplifiers

Abstract As a result of a research and development activity on monolithic low noise structures based on the DMILL process, some basic design criteria have been drawn. These criteria are presented in this paper to show how they can lead to preamplifiers of outstanding noise characteristics that suit applications ranging from calorimetry to tracking and radiation spectrometry.

AToM: the front-end chip for the BaBar silicon vertex tracker detector

This paper describes the readout integrated circuit of the silicon vertex tracker detector for the BaBar experiment at Stanford Linear Accelerator Center. A unique feature of the circuit is its ability to simultaneously amplify and shape signals from 128 microstrip detectors, retain the charge information during the level 1 trigger latency time, and perform sparsification and data transmission over a single serial line. The circuit is composed of two sections. In the analog section signals from the detectors are amplified through a charge sensitive loop, shaped by a CR-RC/sup 2/ filter with digitally selectable peaking time (100 ns, 200 ns, 300 ns or 400 ns) and finally compared to a digitally selectable threshold to perform a range compression. The digital section contains a 193 deep digital pipeline, a three level back-end buffer, two DACs for threshold and calibration voltages, a global control section and a command decoder. The digital section operates at 60 MHz clock speed. Noise measurements at 200 ns peaking time and 3.5 mW total power dissipation per channel yield an equivalent noise charge of 600 el. rms at 12 pF added source capacitance. The chip measures 5.7 mm/spl times/8.3 mm and contains 330 K transistors. A full-scale prototype was fabricated in a 0.8 /spl mu/m, 3-metal rad-soft CMOS process, a second prototype has been characterized using a compatible rad-hard process by Honeywell and the pre-production chip is currently being fabricated.