E. Sexauer

First experience and results from the HERA-B vertex detector system

The HERA-B collaboration is building a detector to realize the ambitious goal of observing CP violation in decays of neutral B-mesons. A central element of the apparatus is the silicon vertex detector used to selectively trigger on these decays in a high charged particle multiplicity background environment and to reconstruct secondary vertices from such decays with high precision. The vertex detector, the supporting infrastructure and first results using prototype detectors are described. Results include imaging of the proton interaction region on the HERA-B target, hit distributions in the detector planes, and alignment of the detectors with each other and the target. ( 1998 Elsevier Science B.V. All rights reserved.

Status of the HERA-B vertex detector

Abstract The HERA-B experiment is a forward magnetic spectrometer with good particle identification for hadrons and leptons designed to study violation of CP symmetry in the neutral B meson system. The silicon vertex detector operates in a high-rate environment similar to the ones expected at LHC. In this paper we report on our R&D on strip detector design, frontend ASICs, mechanical and thermal engineering, low-mass RF shielding of the HERA proton beam and on the status of our reconstruction software. First experiences with last years installation are discussed.

The HERA-B vertex detector system

Abstract The HERA-B experiment is being built to measure CP violation in the B-system using internal targets at the HERA proton storage ring at DESY. This paper presents an overview of its vertex detector which – apart from an additional superlayer – is realized by a system of 20 Roman pots containing seven superlayers of double-sided silicon microstrip detectors that are operated at 10 mm distance from the proton beam in a high-radiation environment.

Performance of the Beetle Readout Chip for LHCb

This paper details the development steps of the 128 channel pipelined readout chip Beetle, which is being designed for the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH detectors of LHCb. Section II. summarizes the Beetle chip architecture. Section III. shows the key measurements on the rst chip version (Beetle1.0 ) which drove the design changes for the Beetle1.1. First performance data of the new chip is presented in section IV., while an outlook on the future test and development of the chip are given in section V.

Radiation hardness of the HERA-B silicon microstrip detectors

SummaryThis paper presents results of a non-uniform irradiation of a single-sided ac-coupledp-on-n siliconstrip detector integrated ona HERA-B detector module. The fluences received by different areas of the detector wafer ranged from less than2 × 1013 MIP/cm2 to a maximum of 2.7 × 1014 MIP/cm2 which allowed a systematic study of the detector performance both in the originaln-type and type-inverted regime as well as in the transition region. Charge collection efficiency, noise, leakage current and full depletion voltage were determined as a function of strip number,i.e. fluence. Full functionality of the whole detector area has been established.

Cluster shapes and cluster sizes in the HERA-B silicon vertex detector

Abstract We report on investigations of shape and size of the clusters on the silicon detectors of the HERA-B vertex detector. The data taken during the commissioning run of 1999 are compared to predictions of model calculations.

Characterisation of a radiation hard front-end chip for the vertex detector of the LHCb experiment at CERN

The Beetle is a 128 channel analog pipelined readout chip which is intended for use in the silicon vertex locator (VELO) of the LHCb experiment at CERN. The Beetle chip is specially designed to withstand high radiation doses. Two Beetle1.1 chips bonded to a silicon strip detector have been tested with minimum ionizing particles. The main goal was to measure the signal-to-noise (S/N) ratio of the Beetle1.1 connected to a prototype VELO detector. Furthermore we investigated the general behaviour of the Beetle1.1. In this note we present the chip architecture, the measured (S/N) numbers as well as some characteristics (e.g. risetime, spillover) of the Beetle1.1 chip. Results from a total ionizing dose irradiation test are reported.

The HERA-B vertex detector

The design of the vertex detector of the HERA-B experiment at DESY is reviewed, and its components are described. The silicon microstrip detectors were optimized for radiation hardness: results from irradiation tests, reproducing the challenging situation in the experiment, are presented. Since spring 1999, much of the system has been installed and is operational. The detector performance and results from track and vertex reconstruction are presented.

SEU Robustness, Total Dose Radiation Hardness and Analogue Performance of the Beetle Chip

The Beetle is a 128 channel readout chip for silicon strip detectors in LHCb. In addition to the pipelined readout path known from the RD20 architecture which can be used either in analogue or binary mode, the Beetle features an additional prompt binary readout path, used for the LHCb pile-up veto counters and a triple-redundant layout of the control logic. It is manufactured in commercial 0.25μm CMOS technology using radiation hard design techniques. In addition to a total dose irradiation with X-rays, an SEU irradiation test with 65 MeV protons was performed with Beetle1.3. The results of this test are presented together with new results from the Beetle versions 1.3, 1.4 and 1.5, which were submitted in the Beetle ER engineering run in May 2004. I. The Beetle Chip Architecture The Beetle [1] is an analogue pipelined readout chip and implements the RD20 front-end architecture [2]. For a fast trigger decision it provides a comparator with prompt binary output signals. Using the comparator output signals instead of analogue front-end signals, the Beetle can alternatively operate in a binary pipelined mode. Figure 1 shows a schematic block diagram of the latest versions Beetle1.2 to 1.5. The chip integrates 128 channels. Each channel consists of a low-noise charge sensitive preampli er, an active now at Stanford Linear Accelerator Centre ynow at Continental Teves AG znow at Dialog Semiconductor GmbH now at Fujitsu Mikroelektronik GmbH CR-RC pulse shaper and a bu er. For capacitive loads 50 pF the chip achieves rise times 25 ns and spillover of 30% of the maximum at 25 ns after the peak, suitable for operation within the LHCb experiment. The chip provides two di erent readout paths. For the binary readout the front-ends output couples to a comparator which features invertable outputs to detect input signals of either polarity and individually adjustable threshold levels. Four adjacent comparator outputs are logically ORed, latched, multiplexed by 2 and routed o the chip via low voltage di erential signaling (LVDS) ports at 80 MHz. The pipelined readout path can operate in either a binary mode by using the comparator outputs or an analogue mode by sampling the front-end bu ers output with the LHC bunch-crossing frequency of 40 MHz. The sampled amplitudes are stored in an analogue memory (pipeline) with a programmable latency of at maximum 160 sampling intervals. This is combined with an integrated trigger bu er of 16 stages. Upon a trigger the corresponding signals stored in the pipeline are transferred to the multiplexer via a resettable charge sensitive ampli er. The number of active output ports is con gurable and allows a readout time of at minimum 900ns per event. The output of a sense channel is subtracted from the analogue data to compensate common mode e ects. On-chip digital-to-analogue converters (DACs) with a resolution of 8 bits generate the bias currents and control voltages. For test and calibration purposes, an adjustable charge injector is implemented on each channel. All bias settings and con guration parameters, e.g. trigger latency, readout mode and readout speed, can be programmed and read back via a standard IC-interface [3]. All digital I/Os, except for the IC-lines and the daisy chain ports, use LVDS signals. The Beetle is designed in a commercial 0.25μm CMOS technology and has a die size of 6:1 5:4mm. The pitch of the analogue input pads is 40.24μm. If no prompt readout is required, the chips can be mounted side-by-side, since no connections to the top and bottom side of the chip are required. This allows an overall pitch of 50 μm matching the readout pitch of typical high resolution silicon strip detectors. In case of the silicon vertex detector, the readout chip will be positioned only 5 cm from the LHC beams, which means that the Beetle has to be radiation hard. The chip is designed to withstand a total dose in excess of 10 Mrad (100 kGy) by taking the following design measures [4]: forced bias currents are used in all analogue stages instead of xed node voltages; enclosed gate structures for NMOS transistors suppress increasing leakage currents under irradiation; a consistent use of guard rings minimises the risk of Single Event Latchup (SEL) [5]. II. Chip Performance Most analogue measurements performed on the previous versions of the Beetle chip have been repeated with Beetle1.3. Measurements of pulse-shapes gain and noise (tab. 1) were conducted, all reproducing the results presented in [6] and [7] very well. Also a comparison of the equivalent noise charges of Beetle1.3 with the results from the Beetle FE 1.1 frontend-only test chip was performed. It showed an only marginal degradation of the noise performance due to the stages of the pipelined readout, corresponding to a 50 e rise in the o set parameter. Table 1: ENC of the Beetle1.3 chip in pipelined operation mode as a function of the Vfs (shaper feedback) control voltage. Vfs Equivalent Noise Charge 0mV 547:7 e + 52:64 e =pF 100mV 539:1 e + 51:89 e =pF 400mV 542:8 e + 49:38 e =pF 1000mV 465:1 e + 45:22 e =pF III. The Beetle ER engineering run A Production Readiness Review (PRR) for the Beetle chip was held at Heidelberg on the 20 of April 2004. It concluded that Beetle1.3 ful ls the requirements of the VeLo and ST detectors, but needs an improved Vertex Locator Silicon Tracker, consisting of Trigger Tracker (TT) and Inner Tracker (TT) detectors discriminator for the application in the VETO. Thus it concluded to place two or three versions of the chip on the reticle for an engineering run. In case of three versions in equal quantities, a subsequent production run would result in 12500 chips/version, while only 3500 are needed to equip the experiment, leaving enough margin for production yield and spares. Therfore it was later on decided to place equal quantities of any chip version on the reticle of the engineering run. Although the Beetle1.3 ful ls the requirements of VeLo and ST, an attempt was made to x the remaining minor problems along with the redesign of the comparator needed in the pile-up VETO. Those include a wrongly encoded pipeline column number parity bit in consecutive readout, some cross talk between the readout lines of the pipeline, and baseline variations between consecutive and non-consecutive event readouts. The foreseen modi cations were categorized into low risk and high risk, and submitted in two di erent designs, in order to maximize the probability of receiving a working chip that satis es all requirements by VETO, VeLo and ST.

Enhanced Radiation Hardness and Faster Front Ends for the Beetle Readout Chip

This paper summarizes the recent progress in the development of the 128 channel pipelined readout chip Beetle, which is intended for the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH detectors of LHCb. De ciencies found in the front end of the Beetle Version 1.0 and 1.1 chips resulted in the submissions of BeetleFE 1.1 and BeetleFE 1.2, while BeetleSR 1.0 implements test circuits to provide future Beetle chips with logic circuits hardened against single event upset (SEU). Section I. motivates the development of new front ends for the Beetle chip, and section II. summarizes their concepts and construction. Section III. reports preliminary results from the BeetleFE 1.1 and BeetleFE 1.2 chips, while section IV. describes the BeetleSR 1.0 chip. An outlook on future test and development of the Beetle chip is given in section V.