E. Verrelli

Forming-free resistive switching memories based on titanium-oxide nanoparticles fabricated at room temperature

In this work, we present symmetric metal-insulator-metal bipolar memristors based on room-temperature deposition of charged titanium-oxide nanoparticles formed in vacuum by a physical process. One of the most striking features of these devices is that they do not require a forming step, which is to be related to protrusions of the top electrode material inside the intrinsically porous nanoparticle films. Furthermore, we report that deposition under substrate biasing conditions strongly affects the structural and electrical properties of the produced titanium oxide nanoparticle films including their bipolar switching behaviour.

Assembly of charged nanoparticles using self-electrodynamic focusing

In this paper, a self-assembly process of charged nanoparticles on a silicon substrate is demonstrated. The self-assembly of the nanoparticles is mainly due to a self-electric-focusing effect caused by the electric field which is created by charged nanoparticles when these are deposited on photoresist patterns. The dynamics of the focusing process and the detailed parameters that affect the focusing effect are discussed both experimentally and by Monte Carlo simulation. The presented technique is a quite simple and effective method to fabricate nanoparticle stripes from different materials.

Investigation of the gate oxide leakage current of low temperature formed hafnium oxide films

In this work, low temperature physically deposited hafnium oxide films are investigated in terms of their electrical properties through measurements and analysis of leakage currents in order to understand the defects behavior in this dielectric material. Two extreme conditions will be presented and discussed: the first one concerns the use of a nearly trap-free hafnium oxide layer, while the second one concerns the use of a hafnium oxide film with a very large amount of electrically active traps. Particular emphasis is given to the detection and comparison of the shallow and deep traps that are responsible for the room temperature leakage of these films. It is shown that by modifying the amount of traps in the hafnium oxide layer, achieved by changing the deposition conditions, the traps energy location is heavily influenced. The nearly trap-free sample exhibits Ohmic conduction at low fields (with activation energies in the range 16–33 meV for low temperatures and 0.13–0.14 eV for higher than ambient temperatures), Poole-Frenkel conduction at high fields (trap depth in the range 0.23–0.38 eV), while at low temperatures and high fields, the Fowler-Nordheim tunneling is identified (estimated barrier height of 1.9 eV). The charge-trap sample on the other hand exhibits Ohmic conduction at low fields (activation energies in the range 0.26–0.32 eV for higher than ambient temperatures), space charge limited current conduction at intermediate fields (exponent n = 3), while at high fields the Poole-Frenkel conduction appears (trap depth in the range 1.63–1.70 eV).

Nickel nanoparticle size and density effects on non-volatile memory performance

In this work, the authors present non-volatile memory devices based on nickel nanoparticles deposited by a novel sputtering process at room temperature and demonstrate and discuss the effect of nanoparticle size and density upon optimum device performance. The devices use a mixed dielectric stack comprised of a silicon dioxide tunneling layer and a hafnium oxide layer formed at low temperature. This allows for fabrication of devices with a relatively small thermal budget and superior performance in terms of memory windows and operating voltages. At voltages as low as 8 V, the memory window of the devices is as large as 5 V. Charge retention measurements confirm the non-volatility of these devices for up to 10 years, and analysis of the leakage currents sheds light on the mechanisms involved that create these charge retention characteristics.

Superhydrophobic SAM Modified Electrodes for Enhanced Current Limiting Properties in Intrinsic Conducting Polymer Surge Protection Devices

Surface interface engineering using superhydrophobic gold electrodes made with 1-dodecanethiol self-assembled monolayer (SAM) has been used to enhance the current limiting properties of novel surge protection devices based on the intrinsic conducting polymer, polyaniline doped with methanesulfonic acid. The resulting devices show significantly enhanced current limiting characteristics, including current saturation, foldback, and negative differential effects. We show how SAM modification changes the morphology of the polymer film directly adjacent to the electrodes, leading to the formation of an interfacial compact thin film that lowers the contact resistance at the Au-polymer interface. We attribute the enhanced current limiting properties of the devices to a combination of lower contact resistance and increased Joule heating within this interface region which during a current surge produces a current blocking resistive barrier due to a thermally induced dedoping effect caused by the rapid diffusion of moisture away from this region. The effect is exacerbated at higher applied voltages as the higher temperature leads to stronger depletion of charge carriers in this region, resulting in a negative differential resistance effect.

Novel conducting polymer current limiting devices for low cost surge protection applications

We report on the development of novel intrinsic conducting polymer two terminal surge protection devices. These resettable current limiting devices consist of polyaniline nanofibres doped with methane sulphonic acid electrochemically deposited between two 55 μm spaced gold electrodes. At normal applied voltages, the low resistance devices act as passive circuit elements, not affecting the current flow. However during a current surge the devices switch from ohmic to non-ohmic behaviour, limiting current through the device. After the current surge has passed, the devices reset back to their original state. Our studies show that a partial de-doping/re-doping process caused by the rapid diffusion of moisture out of or into the polymer film during joule heating/cooling is the underlying mechanism responsible.

Radiation Hardness of Flash and Nanoparticle Memories

Recently, the research for new non-volatile memory in the semiconductor industry has become intense, because current flash memory technologies based on the floating-gate (FG) concept are expected to be difficult to scale down for high density, high performance devices (Lankhorst et al., 2005 ; Ouyang et al., 2004 ; Vanheusden et al., 1997). Therefore, a type of non-volatile memory using nanoparticles (NP) as floating gates has attracted much research attention because of its excellent memory performance and high scalability (Tiwari et al., 1996; Park et al., 2002). By utilizing discrete NP as the charge storage element, NP memory is more immune to local oxide defects than flash memory, thus exhibiting longer retention time and allowing more aggressive tunnel oxide scaling than conventional flash memory (Blauwe, 2002; Hanafi et al., 1996). In NP memory, the device performance and reliability depend on many factors, such as the ability to control NP size, size distribution, crystallinity, area density, oxide passivation quality, and the isolation that prevents lateral charge conduction in the NP layer (Ostraat et al., 2001). Thus, NP memory has driven extensive efforts to form NP acting as charging and discharging islands by various methods. Up to now, several techniques have been developed to form uniform NP in gate oxides. For example, Kim (Kim et al., 1999) employed low pressure chemical vapour deposition (LPCVD) to fabricate Si NP with a 4.5 nm average size and 5×1011cm-2 average density. King (King et al., 1998) fabricated Ge NPs by oxidation of a SiGe layer formed by ion implantation, and demonstrated quasi-nonvolatile memory operation with a 0.4 V threshold-voltage shift. Takata (Takata et al., 2003) applied a sputtering method with a special target to fabricate metal nano dots embedded in SiO. Various NP memory devices have been made to realize the fast and low-power operation of such devices, mostly using Si NP devices surrounded by SiO (Gonzalez-Varona et al., 2003). The programming efficiency has been improved with program voltages reduced far below 10 V, owing to the scaling of tunneling SiO2. Among the advantages related with the NP approach to FLASH technologies, worth to emphasize that owing to the discrete nature of the storage nodes, NP memories are expected to behave much better than standard FG devices in radiation environments. This chapter focuses on this particular issue of the radiation hardness of FLASH, and in particular, NP memory technologies. After a review of the main sources of radiation in space and on earth, we will present a detailed review of the effects of radiation on CMOS electronic devices and discuss the state of the art of radiation effects on standard FG FLASH memories

Structural Characterization of Layers for Advanced Non-volatile Memories

Non-volatile memory cells are the devices with the most aggressive scaling on the market. For this reason the accurate characterization of their layer stacks is of great importance. We present a review of our recent work on a large variety of such stacks, for charge-trap and resistive memories, which have been characterized structurally with Transmission Electron Microscopy and Conducting Atomic Force Microscopy ; we discuss the features of their structure on their function as memory elements.

Resistive switching memory using titanium-oxide nanoparticle films

In this work we present symmetric metal-insulator-metal bipolar memristors based on room-temperature deposition of titanium-oxide nanoparticles (TiO NPs) formed in vacuum by a physical process. We report that deposition under substrate biasing conditions strongly affects the structural and electrical properties of the produced TiO-NP films including their bipolar switching behaviour. The application of an external electric field during deposition enhances the mean size and oxygen content of the TiO NPs as well as the high-to-low resistance (HLR) ratio of the memristive films. Under the substrate-biasing deposition conditions examined so far, we successfully achieved bistable devices with a HLR ratio increased by two orders of magnitude compared to devices using TiO-NP films formed without electric-field assisted NP deposition.

Inorganic Nanoparticles for either Charge Storage or Memristance Modulation

We present prototype memory devices using metallic and metal oxide nanoparticles obtained by a physical deposition technique. The two memory device examples demonstrated concern the use of platinum nanoparticles for flash-type memories and the use of titanium oxide nanoparticles for resistive memories. Both approaches give interesting device memory properties with resistive memories being still in an early exploratory phase.