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Dive into the research topics where Earl T. Cohen is active.

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Featured researches published by Earl T. Cohen.


IEEE Journal of Solid-state Circuits | 1997

A 533-MHz BiCMOS superscalar RISC microprocessor

Cliff A. Maier; James A. Markevitch; Cheryl Senter Brashears; Tim Sippel; Earl T. Cohen; Jim Blomgren; James G. Ballard; Jay C. Pattin; Viki Moldenhauer; Jeffrey A. Thomas; George Taylor

This 533-MHz BiCMOS very large scale integration (VLSI) implementation of the PowerPC architecture contains three pipelines and a large on-chip secondary cache to achieve a peak performance of 1600 MIPS. The 15 mm/spl times/10 mm die contains 2.7 M transistors (2M CMOS and 0.7 M bipolar) and dissipates less than 85 W. The die is fabricated in a six-level metal, 0.5-/spl mu/m BiCMOS process and requires 3.6 and 2.1 V power supplies.


Archive | 1996

Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU

Earl T. Cohen; James S. Blomgren; David E. Richter


Archive | 1994

Master-slave cache system for instruction and data cache memories

Earl T. Cohen; Russell W. Tilleman; Jay C. Pattin; James S. Blomgren


Archive | 1994

Block-based branch prediction using a target finder array storing target sub-addresses

James S. Blomgren; Earl T. Cohen; Brian R. Baird


Archive | 2002

Methods and apparatus for maintaining statistic counters and updating a secondary counter storage via a queue for reducing or eliminating overflow of the counters

Srinivasa Rao Malladi; Earl T. Cohen


Archive | 1994

Address tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuities

James S. Blomgren; Earl T. Cohen


Archive | 1994

Emulation of segment bounds checking using paging with sub-page validity

David E. Richter; Earl T. Cohen; James S. Blomgren


Archive | 1996

Master-slave cache system with de-coupled data and tag pipelines and loop-back

Earl T. Cohen; Jay C. Pattin


Archive | 1996

Slave cache having sub-line valid bits updated by a master cache

Earl T. Cohen; Jay C. Pattin


Archive | 2004

Pipeline scheduler including a hierarchy of schedulers and multiple scheduling lanes

Earl T. Cohen; Robert Olsen; Eugene M. Feinberg; Gregory L. Ries

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