Edoardo Botti

PWM Power Audio Amplifier With Voltage/Current Mixed Feedback for High-Efficiency Speakers

High-efficiency speakers significantly improve electrical to sound power conversion efficiency by reducing the power dissipation over the speaker coil. However, they require some equalization of the input signal. In this paper, a new driving technique based on a pulsewidth-modulation switching amplifier is presented. This exploits a double voltage/current feedback to obtain automatic equalization. Furthermore, the double feedback allows the output resonant filter to be included in the feedback path, compensating for its nonlinearity. Finally, the mixed feedback acts as intrinsic current limiter. Both theoretical analysis and simulations demonstrate that this system is feasible. The results were also confirmed by measurements using a prototype

A high-efficiency 4/spl times/20 W monolithic audio amplifier for automobile radios using a complementary D-MOS BCD technology

In modern auto radios the output power can be as high as four times 20 W. This feature can be obtained with a single monolithic integrated circuit. Such an output power gives rise to a power dissipation, for music, of about 27 W in a standard class-AB amplifier. Since in the auto radio package, space available for the heat sink is limited, efficiency improvement is desirable. To achieve this, the authors present a monolithic quad audio power amplifier, which reduces the power dissipation of the standard class-AB configuration 45% with a music signal. A rail-to-rail output stage and a lossless power switch are implemented in a dedicated complementary DMOS bipolar-CMOS-DMOS (BCD) technology.

A high-speed level shifting technique and its application in high-voltage, synchronous DC-DC converters with quasi-ZVS

This paper presents a level-shifting technique for high-voltage power converter applications. The proposed circuit effectively combines capacitive and active coupling of the input low (high) side signal to the output high (low) side to reduce the propagation delay of the level-shifting operation. By using the resulting circuit, (i) the high-side PMOS switch is driven at high speed and (ii) a quasi-zero voltage switching (ZVS) of the low side NMOS switch is achieved. The circuit has been designed and simulated at the transistor level using a 0.18-μm BCD process. At the high-side, remarkable simulated average level-shifter propagation delay and total driving delay have been achieved: 0.5 ns and 1.9 ns, respectively. The proposed level-shifter consumes 48.5 μA of average current.