Edoardo Fusella

Design automation for application-specific on-chip interconnects

On-chip interconnects provide a vital facility for highly parallel MultiProcessor Systems-on-Chip, particularly in data-intensive applications, where the choice of the underlying communication architecture, tailored on the particular application requirements, is critical to the global performance. This survey focuses on the design automation of a broad class of communication architectures, here referred to as structured on-chip interconnects, the predominant choice in most real-world systems. Such interconnects benefit from well-established standards, CAD compatibility, predictable performance, and are highly scalable for many types of applications. However, in spite of their importance for current MPSoCs and their recent technology advancements, the design methodologies for structured on-chip interconnects have never been exhaustively surveyed so far, unlike application-oblivious interconnect solutions like Networks-on-Chip. The essential aim of this paper is to fill this gap by presenting an extensive review of state-of-the-art design automation techniques for application-specific on-chip interconnects. The paper goes through the main options available for building different on-chip interconnect topologies, discussing the details of hierarchical buses, crossbars, and cascaded crossbars as well as the approaches that can be adopted to formalize the description of such topologies and the related parameters of interest. Then, the paper surveys the most relevant techniques proposed in the literature to analyze a given interconnect solution, i.e. quantify parameters such as latency, bandwidth, area cost, power consumption, operating frequency, followed by an in-depth review of the main approaches for interconnect synthesis, including several advanced aspects such as co-synthesis of memory and communication architectures, joint scheduling and interconnect synthesis, floorplanning, dynamic configuration, multi-path communication. After presenting the above approaches, the paper discusses the potential impact that the body of research in the area of on-chip interconnects may have on current trends and emerging interconnect technologies.

Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects

Multiprocessor Systems-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection topologies potentially meeting given communication requirements, determining various trade-offs between cost and performance. Building interconnects that enable concurrent communication tasks introduces decisive opportunities for reducing the overall communication latency. This work identifies three levels of parallelism at the interconnect level: global parallelism across different independent domains; local or intradomain parallelism, relying on inherently concurrent interconnect components such as crossbars; and interdomain parallelism, where multiple concurrent paths across different local domains are exploited. We propose an automated methodology to search the design space, aimed at maximizing the exploitation of these forms of parallelism. The approach also takes into consideration possible dependencies between communication tasks, which further constrains the design space, making the identification of a feasible solution more challenging. By jointly solving a scheduling and interconnect synthesis problem, the methodology turns the description of the application communication requirements, including data dependencies, into an on-chip synthesizable interconnection structure along with a communication schedule satisfying given area constraints. The article thoroughly describes the formalisms and the methodology used to derive such optimized heterogeneous topologies. It also discusses some case studies emphasizing the impact of the proposed approach and highlighting the essential differences with a few other solutions presented in the technical literature.

PhoNoCMap: An application mapping tool for photonic networks-on-chip

While providing a promising solution for high-performance on-chip communication, photonic networks-on-chip suffer from insertion loss and crosstalk noise, which may severely constrain their scalability. In this paper, we introduce a methodology and a related tool, PhoNoCMap, for the design space exploration of optical NoCs mapping solutions, which automatically assigns application tasks to the nodes of a generic photonic NoC architecture such that the worst-case either insertion loss or crosstalk noise are minimized. The experimental results show significant benefits in terms of insertion loss and crosstalk noise, allowing improved network scalability.

Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems

This work proposes an automated methodology for optimizing FPGA-based many-core interconnect architectures. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible dependencies between tasks under given area constraints. The resulting architecture improves the level of communication parallelism that can be exploited while keeping area costs low. The paper thoroughly describes the proposed approach and discusses a few case-studies showing the impact of the proposed technique.

Minimizing power loss in optical networks-on-chip through application-specific mapping

The next generation of Multiprocessor Systems-on-Chip will require communication facilities that cannot be provided by traditional electronic communication infrastructures. Silicon photonics appears today a promising solution to handle future communication needs thanks to ultra-high bandwidth and extremely low-power consumption. However, designing an optical on-chip network requires addressing several challenges that have no equivalent in the electronic domain. In particular, photonic networks-on-chip suffer from considerable power loss, which affects the network scalability and impacts the performance by constraining the total number of wavelengths and hence the available bandwidth. In this paper, we propose an algorithm which automatically maps the IP cores onto a generic mesh-based photonic NoC architecture such that the worst-case power loss is minimized. As the main contribution, we first formulate the problem of power loss aware mapping and then we propose a genetic algorithm to solve it. Experimental results show that the power loss can be significantly reduced enabling much higher scalability of the on-chip photonic interconnect.

H 2 ONoC: A Hybrid Optical–Electronic NoC Based on Hybrid Topology

Next-generation chip multiprocessors will require communication performance levels that cannot be achieved by traditional electronic ON-chip interconnects. Silicon photonics has recently emerged as a promising alternative to handle future communication needs thanks to the ultrahigh bandwidth and low power consumption. Optical networks-on-chip (ONoCs) are affected by insertion loss and crosstalk noise effects, which constrain the network scalability and impact the power consumption. This paper proposes a hybrid electronic/photonic, hybrid-topology ONoC (H2ONoC), based on a novel architecture aimed at mitigating the above effects. This paper provides a thorough description of the H2ONoC architectures as well as an experimental evaluation based on both synthetic benchmarks and real-world applications. Compared with hybrid mesh- and torus-based network-on-chip architectures, H2ONoC achieves, respectively, 13% and 18% less insertion loss, 32% and 8% less energy consumption under synthetic traffic, 74% and 14% less energy consumption with real applications, as well as better SNR when the system size scales up.

Lighting Up On-Chip Communications with Photonics: Design Tradeoffs for Optical NoC Architectures

Photonic on-chip interconnects are today considered a major pathway to face the insatiable performance demand of manycore computers within tight power constraints. This article provides a broad overview of the opportunities and challenges posed at the architecture level by this new interconnect paradigm. In fact, silicon Photonics introduces many new design tradeoffs, having no electronic equivalent, involving aspects such as wavelength selectivity, physical constraints, and spectral parallelism. As highlighted throughout the paper, getting a cross-cutting understanding of these tradeoffs is essential for harnessing the full potential of on-chip Photonics.

Automated design space exploration for FPGA-based heterogeneous interconnects

The choice of the on-chip communication topology in many systems is of vital importance because it affects the entire inter-component data traffic and impacts significantly the overall system performance and cost. On the other hand, there is today a very large spectrum of on-chip interconnect topologies that potentially meet given communication requirements, determining various trade-offs between cost and performance. This work proposes an automated methodology to search the interconnect design space, avoiding a manual and time consuming try-and-error process. The methodology turns the description of the application communication requirements into an on-chip synthesizable interconnection structure satisfying given area constraints. Targeted at FPGA technologies, the approach combines crossbars and shared buses, connected through bridges, yielding a scalable, efficient structure. The resulting architecture improves the level of communication parallelism that can be exploited, while keeping area requirements low. The paper thoroughly describes the formalisms and the methodology used to derive such optimized heterogeneous topologies. It also discusses some case-studies emphasizing the impact of the proposed approach and highlighting the essential differences with a few other solutions presented in the technical literature.

Crosstalk-Aware Automated Mapping for Optical Networks-on-Chip

Optical networks-on-chip (NoCs) provide a promising answer to address the increasing requirements of ultra-high bandwidth and extremely low power consumption. Designing a photonic interconnect, however, involves a number of challenges that have no equivalent in the electronic domain, particularly the crosstalk noise, which affects the signal-to-noise ratio (SNR) possibly resulting in an inoperable architecture and hence constraining the network scalability. In this article, we point out the implications of application-driven task mapping on crosstalk effects. We motivate the main rationale of our work and provide a formalization of the problem. Then we propose a class of algorithms that automatically map the application tasks onto a generic mesh-based photonic NoC architecture such that the worst-case crosstalk is minimized. We also present a purpose-built experimental setup used for evaluating several architectural solutions in terms of crosstalk noise and SNR. The setup is used to collect extensive results from several real-world applications and case studies. The collected results show that the crosstalk noise can be significantly reduced by adopting our approach, thereby allowing higher network scalability, and can exhibit encouraging improvements over application-oblivious architectures.

On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs

Future many-core systems will require energy-efficient, high-throughput and low-latency communication architectures. Silicon Photonics appears today as a promising solution to achieve these goals. However, the photonics inability to perform inflight buffering and logic suggests the use of Hybrid Photonic-Electronic architectures. In order to exploit the full potential of photonics, it is essential to thoroughly design the Path-Setup architecture, which is the primary source of performance degradation and power consumption. In this paper, we propose a new power-aware path-setup protocol able to put allocated circuits on a stand-by state, rapidly recovering them when needed. We compare in terms of performance and energy consumption some path-setup architectural solutions that differ from each other in the routing algorithm, the path-setup protocol and the deadlock avoidance technique. The results show that the proposed protocol outperforms other solutions in terms of performance and energy efficiency. In addition, this comparison will help many-core system designers to select the most appropriate path-setup architecture according to traffic characteristics and network size.