Edson Luiz Padoin

Performance/energy trade-off in scientific computing: the case of ARM big.LITTLE and Intel Sandy Bridge

Power consumption is one of the main challenges to achieve Exascale performance. Current research trends aim at overcoming power consumption constraints using low-power processors. Although new processors feature sensors that enable precise power measurements, they provide different interfaces to collect data, making it difficult to correlate performance with energy consumption. To overcome this issue, the authors developed a platform-independent tool that collects power and energy data from homogeneous and heterogeneous systems. Using this tool, they provide a detailed comparison between a low-power processor (ARM big.LITTLE) and a high performance processor (Intel Sandy Bridge-EP) using all applications from the NAS parallel benchmarks and a real-world soil irrigation simulator. The results show that the average power demand of Intel Sandy Bridge-EP is within 12.6× to 152.4× higher than ARM big.LITTLE, whereas its average energy consumption is within 1.6× to 7.1× superior. Overall, ARM big.LITTLE presented a better performance/energy trade-off when it takes <9.2× the execution time of Intel Sandy Bridge-EP to solve the same problem.

Evaluating application performance and energy consumption on hybrid CPU+GPU architecture

The High Performance Computing (HPC) community aimed for many years to increase performance regardless of energy consumption. Until the end of the decade, a next generation of HPC systems is expected to reach sustained performances of the order of exaflops. This requires many times more performance compared to the fastest supercomputers of today. Achieving this goal is unthinkable with current technology due to strict constraints on supplied power. Therefore, finding ways to improve energy efficiency become a main challenge on state-of-the-art research. The present paper investigates energy efficiency on heterogeneous CPU+GPU architectures using a scientific application from the agroforestry domain as a case-study. Differently from other works, our work evaluates how the workload of the application may affect energy efficiency on hybrid architectures. Results point out that the power supplier constraints depend also on the workload.

Saving energy by exploiting residual imbalances on iterative applications

The power consumption of High Performance Computing (HPC) systems is an increasing concern as large-scale systems grow in size and, consequently, consume more energy. In response to this challenge, we propose two variants of a new energy-aware load balancer that aim at reducing the energy consumption of parallel platforms running imbalanced scientific applications without degrading their performance. Our research combines dynamic load balancing with DVFS techniques in order to reduce the clock frequency of underloaded computing cores which experience some residual imbalance even after tasks are remapped. Experimental results with benchmarks and a real-world application presented energy savings of up to 32% with our fine-grained variant that performs per-core DVFS, and of up to 34% with our coarsegrained variant that performs per-chip DVFS.

Towards energy-efficient storage servers

As large-scale parallel platforms are deployed to comply with the increasing performance requirements of scientific applications, a new concern is getting the attention of the HPC community: the power consumption. In this paper, we aim at evaluating the viability of using low-power architectures as file systems servers in HPC environments, since processing power is of less importance for these servers. We present a performance and energy efficiency study of such low-power servers when compared to conventional architectures. Our results indicate that the low-power alternative could be a viable choice to save energy by up to 85+ while not compromising on performance, specially for read-intensive workloads. We show the low-power server provides 7 times more energy efficiency to the system while running a real application from the seismic wave propagation field.

GreenHPC: a novel framework to measure energy consumption on HPC applications

Energy consumption on systems that have a continuous power source is tightly-related to both the computing time of an application and its required CPU load. Considering the scope of HPC applications which commonly have a time precision in nano or milliseconds, we observe a lack of systems that combine appropriate sampling rate, low intrusiveness and low cost. In this context, this article presents a model called GreenHPC that uses a hall effect sensor to precisely capture current with an arbitrary timeslice on HPC applications. Its scientific contribution relies on analyzing the energy consumption at a cluster scale, without application intrusiveness, showing the impact of maintaining idle nodes or turning them off for energy saving. Furthermore, considering the use of GreenHPC over the execution of a seismic wave application, we also present the number of employed processors which present the best energy consumption index. Finally, we have used the obtained results to infer a model to estimate energy consumption of HPC applications. All the developed work has a special concern on reproducibility, so all data and hardware schematics are available for download at 1.

Energy efficiency and I/O performance of low-power architectures: Energy efficiency and I/O performance of low-power architectures

This paper presents an energy efficiency and I/O performance analysis of low‐power architectures when compared to conventional architectures, with the goal of studying the viability of using them as storage servers. Our results show that despite the fact the power demand of the storage device amounts for a small fraction of the power demand of the whole system, significant increases in power demand are observed when accessing the storage device. We investigate the access pattern impact on power demand, looking at the whole system and at the storage device by itself, and compare all tested configurations regarding energy efficiency. Then we extrapolate the conclusions from this research to provide guidelines for when considering the replacement of traditional storage servers by low‐power alternatives. We show the choice depends on the expected workload, estimates of power demand of the systems, and factors limiting performance. These guidelines can be applied for other architectures than the ones used in this work.

Using Power Demand and Residual Load Imbalance in the Load Balancing to Save Energy of Parallel Systems

Abstract Power consumption of the High Performance Computing (HPC) systems is an increasing concern as large-scale systems grow in size and, consequently, consume more energy. In response to this challenge, we have develop and evaluate new energy-aware load balancers to reduce the average power demand and save energy of parallel systems when scientific applications with imbalanced load are executed. Our load balancers combine dynamic load balancing with DVFS techniques in order to reduce the clock frequency of underloaded computing cores which experience some residual imbalance even after tasks are remapped. The results show that our load balancers present power reductions of 7.5% in average with the fine-grained variant that performs per-core DVFS, and of 18.75% with the coarse-grained variant that performs per-chip DVFS over real applications.

Performance Prediction of Acoustic Wave Numerical Kernel on Intel Xeon Phi Processor

Fast and accurate seismic processing workflow is a critical component for oil and gas exploration. In order to understand complex geological structures, the numerical kernels used mainly arise from the discretization of Partial Differential Equations (PDEs) and High Performance Computing methods play a major in seismic imaging. This leads to continuous efforts to adapt the softwares to support the new features of each architecture design and maintain performance level. In this context, predicting the performance on target processors is critical. This is particularly true regarding the high number of parameters to be tuned both at the hardware and the software levels (architectural features, compiler flags, memory policies, multithreading strategies). This paper focuses on the use of Machine Learning to predict the performance of acoustic wave numerical kernel on Intel Xeon Phi many-cores architecture. Low-level hardware counters (e.g. cache-misses and TLB misses) on a limited number of executions are used to build our predictive model. Our results show that performance can be predicted by simulations of hardware counters with high accuracy.

Exploration of load balancing thresholds to save energy on iterative applications

The power consumption of High Performance Computing systems is an increasing concern as large-scale systems grow in size and, consequently, consume more energy. In response to this challenge, we proposed two variants of a new energy-aware load balancer that aim at reducing the energy consumption of parallel platforms running imbalanced scientific applications without degrading their performance. Our research combines Dynamic Load Balancing with Dynamic Voltage and Frequency Scaling techniques in order to reduce the clock frequency of underloaded computing cores which experience some residual imbalance even after tasks are remapped. This work presents a trade-off evaluation between runtime, power demand and total energy consumption when applying these two energy-aware load balancer variants on real-world applications. In this way, we can define which is the best threshold value for each application under the total energy consumption, total execution time or the average power demand focus.