Edward A. Rietman

Back-propagation learning and nonidealities in analog neural network hardware

Experimental results from adaptive learning using an optically controlled neural network are presented. The authors have used example problems in nonlinear system identification and signal prediction, two areas of potential neural network application, to study the capabilities of analog neural hardware. These experiments investigated the effects of a variety of nonidealities typical of analog hardware systems. They show that network using large arrays of nonuniform components can perform analog communications with a much higher degree of accuracy than might be expected given the degree of variation in the networks elements. The effects of other common nonidealities, such as noise, weight quantization, and dynamic range limitations, were also investigated.

Use of neural networks in modeling semiconductor manufacturing processes: an example for plasma etch modeling

System modeling using the plasma etch process is used as a vehicle to demonstrate the application of adaptive nonlinear neural networks in complex process modeling. The system is an active manufacturing process for tantalum silicide plasma gate etching. The model is for a single process recipe, a single technology (1.25 mu m), and a single machine. The model uses a few process signatures to successfully predict the oxide remaining (within 7 AA). The model is pattern density invariant. It is demonstrated that the backpropagation algorithm is adequate for building neural network models of complex nonlinear processes using production databases. The neural network model has a correlation of 0.68 while the statistical model has a correlation of 0.45. >

A neural network model of a contact plasma etch process for VLSI production

The etch process for preparation of via contacts in VLSI manufacturing is described along with a neural network model of the process. The neural network is a two hidden layer network (23-3-3-1) trained by error back-propagation. The input variables to the model are the mean values of set-point fluctuations for the control variables of the plasma reactor, and the output is the oxide thickness remaining after the etch. The model is thus abstracted by several levels of reality. The real-world process results in a film thickness about 24 000 /spl Aring/ and a standard deviation of about 730 /spl Aring/. We demonstrate that a neural network model can predict the post-etch oxide thickness to within 480 /spl Aring/ and that inherent noise in the training/testing data is 416 /spl Aring/. We also demonstrate that the dc bias and the etch times are the most important variables to determine the final product quality.

Pre-production results demonstrating multiple-system models for yield analysis

We have assembled an integrated view of the entire via manufacturing process. This integrated study includes five key plasma processes that culminate in the production of vias on CMOS wafers. There are essentially no linear cross-correlations between the processing steps and there are no linear correlations between the individual process steps and the yield for vias, as measured by the resistance between metal-one (M1) and metal-two (M2). Using a neural network, we demonstrate that the key processing steps to determine the M1M2 resistance are the thick oxide deposition and the anisotropic via etch. Of lesser significance are the etchback planarization, an isotropic etch and plasma enhanced tetra-ethoxy silane (PETEOS) deposition. Keeping in mind that there are five processing steps, the numerical value of M1M2 resistance can be predicted ahead of time, before completion of all five processes. This prediction can be done to an accuracy of about 1 /spl Omega/. By using adaptive neural networks, the intelligent agents can modify their predictive behavior with respect to process changes effected by the engineering staff. Our pre-production demonstration suggests that these programs could be used in feedback and feedforward control for production yield.

Amorphous silicon photoconductive arrays for artificial neural networks.

We have demonstrated an electronic implementation of an artificial neural network with 14,400 synaptic connections of variable strength using an array of a:Si:H photoconductors. This neural network has been configured as a Hopfield associative memory, and used to successfully perform simple pattern recognition. Our initial results suggested that, using these a-Si:H photoconductive arrays as the optically programmable synaptic matrix, neural networks of large sizes may be achieved. This paper describes the fabrication and device characteristics of a-Si:H photoconductive arrays as well as a model application of a neural network.

A study on failure prediction in a plasma reactor

We use several approaches to demonstrate that neural networks can detect precursors to failure. That is, they can detect subtle changes in the process signals. In some cases these subtle changes are early warnings that a subsystem failure is imminent. The results on detection of precursors and faults with various types of time-delay neural networks are discussed. We also measure the noise inherent in our database and place bounds on neural network prediction in the presence of noise. We observe that the noise level can be as high as 40% for detection of failures and can be at 30% to still detect precursors to failure. We note that although self-organizing networks for classification of faults seems like a good idea, in fact they do not perform well in the presence of noise. Lastly, we show that neural networks can induce, or self-build, Markov models from process data and these models can be used to predict system state to a significant distance in the future (e.g., 100 wafers).

A genetic algorithm for low variance control in semiconductor device manufacturing: some early results

Genetic algorithms are a computational paradigm modeled after biological genetics. They allow one to efficiently search a very large optimization space for good solutions. In this paper we describe the use of a genetic algorithm for developing robust plasma etch recipes that reduce the variance about a target mean and allow the dc bias to drift within 15% of a nominal value. The tapered via etch process in our production facility results in a oxide films of about 7093 /spl Aring/ and a standard deviation of 730 /spl Aring/. In simulations using real production data and a neural network model of the process our new recipes have reduced the standard deviation below 200 /spl Aring/. These results indicate that significant improvement in the process can be realized by applying these techniques.

A system model for feedback control and analysis of yield: A multistep process model of effective gate length, poly line width, and IV parameters

We present a large system model capable of producing Pareto charts for several yield metrics, including effective channel length, poly line width, I/sub on/ and I/sub sub/. These Pareto charts enable us to target specific processes for improvement of the yield metric(s). Our neural network model has an accuracy of 80% and can be trained with a small data set to minimize the feedback time in the control loop for the yield. The system we describe has been implemented in a Lucent Technologies microelectronics lab in Orlando, FL.

DYNAMIC IMAGES OF PLASMA PROCESSES : USE OF FOURIER BLOBS FOR ENDPOINT DETECTION DURING PLASMA ETCHING OF PATTERNED WAFERS

By monitoring various process parameters (e.g., applied rf power, flow rate of gases, etc.) as a function of time, we show that Fourier series decomposition of the values of those parameters, at each time step, plotted on polar coordinates, gives closed curves representing the state of the plasma and the activity on the wafer. A change of the shape of the “blob” is a signature of the endpoint. The technique was successfully applied on TiN/poly-Si, WSix, and doped poly-Si gate etch, and contact etch processes. Moreover, the method is reproducible from wafer to wafer and can be used easily by inexperienced operators to spot endpoint in plasma processes.

A production demonstration of wafer-to-wafer plasma gate etch control by adaptive real-time computation of the over-etch time from in situ process signals

An adaptive nonlinear controller for wafer-to-wafer plasma etch control is described. It uses real-time process signatures and historical data from a relational database for a computation of the over-etch time for the current wafer etching within the reactor. For an MOS gate etch the standard deviation of the oxide thickness between the gate and the source (or drain) is in the range of 10 /spl Aring/. This is comparable to open-loop control or timed etch where the operator selects the ideal over-etch time. The controller has thus achieved a minimum of human equivalence and often performs better by 40%. >