Edward H. Nicollian

Mechanism of negative-bias-temperature instability

Although negative‐bias‐temperature instability in metal‐oxide‐semiconductor integrated circuits has been minimized empirically, the exact mechanism is unknown. We argue in this paper that the mechanism of negative‐bias‐temperature instability can be modeled by a first‐order electrochemical reaction between hydrogenated trivalent silicon, a neutral water‐related species located in the oxide near the Si‐SiO2 interface, and holes at the silicon surface to form neutral trivalent silicon and a positively charged water‐related species. To show that such a reaction describes the phenomenon, we show that (1) water must be present in the oxide near the Si‐SiO2 interface, (2) induced interface and oxide‐fixed charge densities are equal, (3) the saturation interface‐trap and oxide‐fixed charge densities depend on the initial hole concentration at the silicon surface or aging field, (4) the buildup of these charge densities follows first‐order reaction kinetics, and (5) time constants for this charge buildup are inde...

Slow conductance oscillations in nanoscale silicon clusters of quantum dots

At fixed reverse bias voltages of a diode structure consisting of nanoscale silicon particles embedded in an amorphous SiO2 matrix, conductance oscillation in time is observed on some samples at room temperature. Possible mechanisms of the conductance oscillations include the exchange of electrons between the quantum confined states coupled to localized defects and the charge state of these defects. The precise origin of the observed oscillations has not been identified.

Electrical properties of a silicon quantum dot diode

The electrical properties of a diode consisting of nanoscale silicon quantum dots embedded in an amorphous silicon dioxide matrix are presented in terms of an equivalent circuit. The division of the applied bias between the quantum dot‐silicon dioxide layer and the nondegenerate silicon substrate, and the magnitude of the coulomb blockade due to charged electron traps in the quantum dots are determined from the equivalent circuit. Coulomb blockade is important because it contributes to both the large energy separation between successive quantum states, and the applied bias at which quantum effects are first observed.

A new model for the thermal oxidation kinetics of silicon

A model is presented which reasons that the thermal oxidation of silicon is surface reaction limited, and that the reaction rate is controlled by the viscous flow of newly forming oxide to accommodate the volume expansion that occurs when silicon oxidizes. The SiO2 must form at silicon lattice sites and therefore epitaxially. This thermody-namically unstable epitaxial structure reconfigures and this reconfiguration results in an increase of the average viscosity of the oxide. The continual increase of average oxide viscosity accounts for the continual decrease in oxidation rate with time. A mathemat-ical analysis based on this model is used to derive the simple power law x = atb relating oxide thickness, x, to oxidation time, t which has been shown previously to model phe-nomenologically all of the extant dry oxidation data.1 The physical significances of the coefficient a and exponent b are obtained by the interpretation of the x vs t data in the literature in terms of this mathematical analysis.

Accurate measurement of trivalent silicon interface trap density using small signal steady‐state methods

The high–low‐frequency capacitance method for determining the interface trap density is widely used in studying the effects of ionizing radiation on thermally grown SiO2, and in verifying the trivalent silicon interface traps first discovered in electron paramagnetic resonance studies. It is shown that the high–low‐frequency capacitance method gives fictitious interface trap density peaks because of the departure of the 1‐MHz high‐frequency capacitance from the ideal high‐frequency capacitance. This method gives accurate values of the interface trap density near the center of the silicon band gap, but for a given high frequency, the range of band‐gap energy over which accurate values are obtained decreases with increasing interface trap density. Interface trap density is obtained over a band‐gap energy range with an accuracy that is independent of interface trap density from a comparison of the measured and calculated slopes of gate bias versus equilibrium band‐bending curves using the Q‐C (charge‐capacit...

Low-temperature annealing of As-implanted Ge

Furnace annealing (FA) and rapid thermal anealing (RTA) of As75‐implanted Ge is studied and contrasted. Activation has been observed in furnace‐annealed samples at 500 °C. Rapid thermally annealed samples show activation at 575 °C and thereafter. Diffusion effects are significant during FA above 575 °C, while RTA is accompanied with very little dopant diffusion. Damage annealing is best in the FA samples as indicated by the mobility profiles. A dual process such as a 430 °C‐FA/650 °C‐RTA offers best results for activation, especially in the case of low‐dose implants (∼97%). Carrier concentration profiles resemble theoretical implant profiles except near the surface where a region of high concentration is observed.

Resonant tunneling in microcrystalline silicon quantum box diode

STRACT Resonant tunneling in threedimensionally quantum confined (3DQC) microcrystalline silicon surrounded by amorphousSi02(aSiO barriers is experimentally observed. Unlike quantum confinement in lower dimenstons charge accumulation in 3DQC silicon box results in large shifts of the discrete energy states with conductancegate voltage measurements.

Passivation of defects in polycrystalline superlattices and quantum well structures

In order to broaden the available materials for superlattices and quantum well structures, well‐passivated polycrystalline semiconductors and amorphous oxides such as pc‐Si/a‐SiO2, pc‐Ge/a‐GeO2 (pc: polycrystalline; a: amorphous) are proposed. Crucial in maintaining long scattering length involves the passivation of pc‐Si (polycrystalline silicon) and pc‐Ge. Specific means to passivate grain boundaries are discussed which consist of the use of the common dangling bond teminator, hydrogen, as well as amorphous oxides and other amorphous materials. This unique procedure may be extended to the entire group III‐V semiconductors such as polycrystalline GaAs and InP.

LAPLACE TRANSFORM METHOD OF MEASURING THE DISTRIBUTION OF SI-SIO2 BARRIER HEIGHTS : BASIC PRINCIPLES

The electronegativity difference between silicon and SiO2 produces a dipole layer at the Si–SiO2 interface which determines the barrier height between the silicon and SiO2 conduction bands. Because thermally grown SiO2 is amorphous, the alignment of these dipoles with respect to each other fluctuates resulting in a barrier height distribution. Photon‐assisted injection of electrons into the thermally grown gate oxide of a metal‐oxide‐semiconductor field‐effect transistor is used to extract this distribution by experiment. The ratio of the injected gate current to the short‐circuit source–drain photocurrent collected under the gate is shown to be the Laplace transform of the barrier height distribution. By inverting the Laplace transform, measured under the specific experimental conditions described, the barrier height distribution is found to be Gaussian. The average zero‐field barrier height is found to be 3.5 eV with a standard deviation of 0.64 eV measured in the oxide over a plane parallel to the Si–S...

Laplace transform method of measuring the distribution of Si–SiO2 barrier heights: Implementation

Using the Laplace transform method, the specific experimental conditions are given under which the extraction of a Gaussian distribution of barrier heights, in the Si–SiO2 heterojunction, is based. Specifically described are: (1) the maintenance of a constant oxide field despite oxide charging; (2) the determination of the substrate field produced by the backgate bias; (3) the extraction of the short‐circuit source–drain photocurrent collected under the gate from the total short‐circuit photocurrent which is the sum of the photocurrents collected under the gate and by the source–drain junctions; (4) the minimization of inversion layer free‐carrier absorbtion to make the amount of incident light that penetrates the substrate independent of both the gate and backgate bias; and (5) the implementation of the measurement system to extract the barrier height distribution.