Edward W. Chencinski

S/390 parallel enterprise server CMOS cryptographic coprocessor

As the Internet becomes the basis for electronic commerce, and as more businesses automate their data processing operations, the potential for unauthorized disclosure of sensitive data increases. On-line databases are becoming increasingly large and complex. Sensitive data is transmitted on communication lines and often stored off-line. As a result, the efficient, economical protection of enterprise-critical information is becoming increasingly important in many diverse application environments. The protection required to conduct commerce on the Internet, provide data confidentiality, and provide user authentication can be achieved only by cryptographic services and techniques. The high-speed, physically secure IBM S/390® CMOS Cryptographic Coprocessor for S/390 Parallel Enterprise Servers™, together with the IBM Integrated Cryptographic Service Facility (ICSF), an IBM licensed program for the OS/390® operating system, provides the ability to encrypt and decrypt data, generate and manage cryptographic keys, perform PIN operations, and perform other cryptographic functions dealing with data integrity, digital signatures, and key exchange.

IBM system z10 I/O subsystem

The performance, reliability, and functionality of a large server are greatly influenced by the design characteristics of its I/O subsystem. The critical components of the IBM System z10™ I/O subsystem have, therefore, been significantly improved in terms of performance, capability, and cost. The first-order network has been redesigned from the long-evolved enhanced self-timed interface (eSTI) links to utilize InfiniBand™ links. A redesign of the host logic of I/O chips and the fiberoptic interfaces within the links made it possible to introduce InfiniBand-based IBM Parallel Sysplex® links. A broad range of legacy I/O channels have been carried forward to connect through InfiniBand, and a foundation has been laid for new channel types of improved functionality and performance. The first such hardware channel to be introduced is the next generation of Ethernet-virtualization data routers. A new and methodical recovery structure has been designed to ensure consistent, extensive support of reliability, availability, and serviceability. A building-block-oriented design process has been developed to enable the innovations that made these advances possible. Finally, a new performance verification methodology has been introduced to ensure that the system and subsystem designs are balanced to make effective use of the increased capacity.

The structure of chips and links comprising the IBM eServer z990 I/O subsystem

The performance of large servers is to a high degree determined by their I/O subsystems. In the z990 server, nearly all of the components in the I/O path have been considerably improved in performance, capability, and cost. A 2-GB/s enhanced self-timed interface (eSTI) was introduced which is capable of absorbing the ever-increasing data rates of modern high-speed adapters. The I/O bandwidth available from a single node (three memory bus adapter, or MBA, chips, each with four eSTI ports) now equals 48 GB/s. As a consequence, both the MBA chip and the STI multiplexer switch (STI switch) chip had to be completely redesigned. In addition to these two chips, this paper describes the eSTI design itself and the Sweep chip, which integrates the function of four bidirectional adapter chips, one switch chip, and a clock chip.

Advances in the IBM z13 I/O function and capability

The IBM z13™ introduces a number of significant improvements in the I/O subsystem relative to the IBM zEnterprise™ EC12. This includes advancing the I/O drawer infrastructure to implement generation 3 (Gen 3) of the Peripheral Component Interconnect Express® (PCIe®) links and switches. For the first time on this platform, the PCIe ports are placed directly within the IBM z13 processor itself, reducing latency by avoiding the necessity of using hub chips that have traditionally been implemented for routing and expansion of the PCIe infrastructure. Portions of the processor chip have been reserved to implement the functionality that would previously have resided on these separate hub chips. Traditional I/O features such as Fiber Connection (FICON®), Fibre Channel Protocol (FCP), Open System Adapter (OSA), Crypto Express, and Flash Express are provided with enhanced functionality in the PCIe I/O drawer. The PCIe infrastructure has created the opportunity to integrate additional native PCI adapters. This is further exploited with the use of Single Root I/O virtualization (SR-IOV) capability on a Remote Direct Memory Access over Converged Ethernet (RoCE) Express adapter, which now provides shared exploitation of the facilities within this adapter. An adapter utilizing field programmable gate arrays has been developed to provide compression acceleration in the z13 and forms a foundation for additional varieties of acceleration in the future.

Flash storage integration in the IBM System z EC12 I/O drawer

Flash storage is integrated for the first time on System z® as a card in the EC12 I/O drawer. This provides a number of functions and benefits in the immediate product, in addition to laying a foundation for further system benefits in future generations of System z systems. Enabling flash MLC (multilevel cell) technology as SCM (storage class memory) in an enterprise-class product required myriad diverse individual technological advances, together with a series of system design features. Extreme care and attention were paid to ensure that the required level of System z reliability was maintained. As with legacy I/O, the programming interface is subchannel-based. The subchannel programming interface is expanded with new architecture via the extended asynchronous-data-move facility. Operating system changes were required to enable exploitation of the features that this new system technology offers. These individual hardware, firmware, and software design aspects are described in this paper, along with the overall functionality and system-level value of this new technology.

Functional verification of a frequency-programmable switch chip with asynchronous clock sections

An integral part of the IBM eServerTM z990 I/O subsystem is the self-timed interface (STI) switch chip. The STI switch is an application-specific integrated circuit (ASIC) designed to provide high I/O connectivity and high bandwidth within the system. The complexity of the functional verification of the STI switch chip is inherent in the implementation of seventeen logical clock domains and the support of six different STI interfaces with programmable frequencies. The logic within these clock domains is connected via asynchronous interfaces. This paper describes the methodology to verify the functionality of the switch chip with various STIs by introducing a combination of verification techniques. This involves random biased stimulus generation, automated result prediction checking, and the use of cycle simulation to stress the logical design. The cycle simulation required new techniques to model equivalent behavior in order to verify the correct integration of nondigital components on the chip. Advanced methods were implemented to ensure correctness of the frequency-dependent design units and functionality across the asynchronous interfaces. A single verification environment was developed, providing the flexibility to seamlessly support the different levels of design abstraction and uncover the design errors at the appropriate level.