Edwin van der Heijden

A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip

A compact two-stage differential cascode power amplifier is designed and fabricated in 45 nm standard LP CMOS. The cascode configuration, with the common gate device placed in a separate P-well, provides reliable operating condition for the devices. The amplifier shows 20 dB small-signal gain centered at 60 GHz with a flat frequency response and 1-dB bandwidth of 10 GHz. The broadband large-signal operation is also ensured by providing constant load resistance to both stages over the entire band and coupling them with a dual resonance matching network. The chip delivers 11.2 dBm output power at 1-dB compression and up to 14.5 dBm power in saturation. The power amplifier operates with 2 V supply and draws 90 mA total current which results in 14.4% maximum PAE. The output third order intercept point is measured to be 18 dBm for two-tone measurement at 60 GHz with 0.5 GHz, 1 GHz and 2 GHz frequency separations.

A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications

This work presents a 21.7-to-27.8GHz frequency synthesizer in a 45nm CMOS process that combines a tuning range of 24.8%, a residual phase modulation of 2.57°rms (with integrated phase noise from 100kHz to 100MHz), and a total power dissipation of 40mW. Combined with a frequency multiplier-by-two circuit and a divider-by-two circuit in a sliding-IF configuration, the PLL provides the four source frequencies required by the IEEE 802.15.3c 60GHz communication standard. In addition, the attained phase noise makes it suitable for microwave links with higher-order modulation schemes used as the back-bone for 3G/LTE base-station networks.

A 60GHz digitally controlled RF-beamforming receiver front-end in 65nm CMOS

Phased arrays form a crucial step towards high data rate 60GHz wireless communication. This paper presents a fully integrated digitally controlled 60GHz RF-beamforming receiver front-end in CMOS. Using digitally controlled active phase shifters, each path of the scalable architecture achieves 10dB power gain, 7.2dB noise figure, a 360° phase shift range in 22.5° steps at 61GHz, and a 3dB-bandwidth of 5.4GHz, while only dissipating 78mW in each path. Chip area is 1.6mm2.

A 60GHz Miller Effect Based VCO in 65nm CMOS with 10.5% Tuning Range

This paper presents a 60 GHz voltage controlled oscillator implemented in conventional 65 nm CMOS technology. This VCO employs an alternative tuning system based on the Miller capacitance instead of conventional varactors. The presented VCO has a tuning range of 10.5 % and operates in the frequency range of 59.5 GHz to 66.1 GHz. It has an output power of -13 dBm and a phase noise of 80 dBc to -85 dBc/Hz @ 1 MHz over its entire range. The figure-of-merit (FOM) of this VCO is -162 dB.

Wideband cancellation of second order intermodulation distortions in a 60GHz zero-IF mixer

The 1GHz target IF bandwidth of 60GHz zero-IF mixers makes conventional single- and double-parameter tuning methods ineffective for suppression of second-order intermodulation distortions across the whole IF band. In this paper a three-dimensional circuit parameter tuning method is used to address this problem. Output resistance, output capacitance, and gate biasing of the switching pairs are three parameters chosen for tuning. The mixer is designed and fabricated in CMOS 45nm technology. Measurement results show that the IMD2 tones across the whole 1GHz IF band can be suppressed simultaneously to within the noise level. The measured power conversion gain, IIP3 and typical corrected IIP2 of the mixer are 7dB, −7dBm and 27dBm, respectively.

A 30GHz integrated time-division multiplexing front-end for phased-array applications in SiGe

This paper presents a fully integrated receiver front-end for time-division multiplexing phased-array system. The 30GHz front-end includes a low-noise amplifier (LNA), a 4:1 multiplexer, a mixer, and a clock sequencer. The circuit has been implemented in a 0.25μm, 130GHz-fT SiGe process. The front-end shows a input reflection coefficient (S11) of −20dB, a minimum measured LNA-Multiplexer noise figure (NF) of 4.1dB, and a maximum conversion gain (CG) of 18.9dB at 30GHz. Measurements show a 1dB input compression point of −32.3dBm, a third order intercept point (IIP3) of −22dBm, and a channel isolation of 23dB at 30GHz. This system reduces receiver power consumption by reducing ADC numbers.

MEEC Models for RFIC Design Based on Coupled Electric and Magnetic Circuits

This paper proposes the use of coupled electric and magnetic circuits in the schematic models of high frequency integrated circuits, as an effective method to model the global inductive effects and coupling. These pairs of coupled circuits, called magneto-electro-equivalent circuit (MEEC) models, are obtained by partitioning the computational domain into several subdomains, each having its own electromagnetic field regime. The model reduction method we propose can be used not only to derive the full coupled electric and magnetic circuit model of a device starting from its layout, but also to correct the electric schematic by adding inductive parasitic effects. The MEEC approach uses special boundary conditions-called magnetic/electric hooks-on the interfaces between the subparts in which the computational domain is partitioned. The success of the correct extraction of inductive effects rely on the terminal reduction, i.e., the correct placement of magnetic hooks on the interfaces. In order to find this placement, a heuristic approach based on IC layout analysis is proposed. In order to consider the parasitic inductive couplings, the electric schematic circuit graph is enhanced with geometric information from the layout (e.g., node coordinates). The MEEC-based approach is validated for a real example of a low noise amplifier. Its initial layout design proved to be wrong only after the fabrication and characterization of the first prototype. The use of the inductive parasitic extraction tool, based on the MEEC approach, would have prevented this. MEEC is an alternative approach to vector potential equivalent circuit, with respect to which advantages and disadvantages are discussed.