Edwin W. Greeneich

An analytical model for the gate capacitance of small-geometry MOS structures

An analytical formulation of the gate capacitance of MOS structures which takes into consideration the effects of electrode thickness and lateral gate dimensions is presented. Results are presented in normalized form covering a wide range of typical device dimensions.

An appropriate device figure of merit for bipolar CML

The effects of base resistance, base transit time, and junction capacitances play a key role in the propagation delay of high-speed bipolar logic gates. A simple device figure of merit for transistors used in current mode logic (CML) circuits, based on minimum propagation delay, is developed. This delay is derived from the large-signal 3-dB cutoff frequency of the CML gate. Results are shown to be applicable for a wide range of device and circuit parameters.<<ETX>>

Vertical n-p-n bipolar transistors fabricated on buried oxide SOI

Vertical n-p-n bipolar transistors have been fabricated in silicon-on-insulator (SOI) films prepared by buried oxide implantation. Electrical device characteristics are shown to be comparable to those obtained on devices fabricated in bulk silicon, indicating no significant degradation owing to the buried oxide layer. Dielectric isolation in excess of 1011Ω.cm and µ 3 × 106V/cm is measured.

Low-power transistor-string and new rail-to-rail comparator in A/D converter

A p-MOS transistor-string and a new rail-to-rail comparator are introduced. Transistor-strings for ADC save chip area with good voltage-matching behavior. Also, the new rail-to-rail comparator improved the DC gain by a factor of 2 compared to conventional rail-to-rail comparator when the reference voltages are 0 and V/sub DD/.

Body effect compensated switch for low voltage switched-capacitor circuits

In order to reduce distortion due to the threshold voltage variations of an NMOS switch by the input signal, a novel low-voltage switch that compensates the body effect is proposed. The linearity performance of the proposed circuit is confirmed by simulation with a 0.5 /spl mu/m standard CMOS technology (V/sub tn0/=0.7 V, V/sub tp0/=1.0 V). Simulations with HSPICE indicate better performance of the total harmonic distortion (THD) is achieved using the proposed circuit in a first-order non-inverting switched-capacitor (SC) low pass filter operating with a single 1.5-V power supply.

A current-controlled oscillator coarse-steering acquisition-aid for high frequency SOI CMOS PLL circuits

A self-adjusting frequency control circuit for a high-speed phase-locked loop (PLL) system is designed for implementation in a 0.25 /spl mu/m SOI CMOS technology. This coarse-steering circuit uses a current sensor to indirectly detect the running frequency of the VCO/ICO and combine the result generated from a simple frequency comparator to determine an active frequency control range for the PLL. The entire circuit has been simulated with a wide frequency range of 850 MHz and a power supply voltage of 1.8 volts on HSPICE.

Design of a 1-V High-Frequency Bipolar Operational Amplifier

This paper presents the design of a low-voltage high-frequency operational amplifier implemented in bipolar technology. The minimum power supply voltage for this amplifier can be as low as 0.9 V, so it is suitable for portable equipment applications. The design emphasis is on the high frequency response. A pole-zero cancellation compensation technique and a special low-voltage design gives a simulated cutoff frequency of about 175 MHz with a 50° phase margin at a power supply voltage of ±0.5 V with a 10 kΩ load resistance; the low-frequency voltage gain is 110 dB. The common-mode input range includes, and can exceed, the negative supply voltage by about 400 mV. A complimentary class-B type output stage enables the output voltage to reach both supply rails within about 100 mV without significant signal distortion. This amplifier dissipates 875 μW.

Base spreading resistance of polysilicon self-aligned bipolar transistors

The base spreading resistance and its variation with current are analyzed for bipolar transistor structures in which the extrinsic base contact region extends completely around the emitter region. An analytic expression for the resistance is derived that represents the limiting case of a small rectangular emitter structure with corner-rounding. Results of the analysis show good agreement with numerical simulation results. This approach has application in the modeling of modern small-geometry bipolar transistors. >

Wide operating-range acquisition technique for PLL circuits

A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 /spl mu/m CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE.

Fast pipelined A/D converter in CMOS technology

In this paper, a new 8-bit pipelined A/D converter which has been fabricated in n-well CMOS technology is introduced. Even though a fully, differential op-amp is preferred to obtain a high power supply rejection ratio, a single-ended op-amp is implemented in the A/D converter to investigate the speed performance of the new pipelined A/D converter. The main purpose of this work is to compare the conventional pipelined A/D converter with the new one in terms of speed. According to experiments, the new pipelined converter improves the speed by a factor of 2.5 compared to conventional pipelined A/D converters because it uses more parallel schemes. With the architecture, one can build fast low-power A/D converters in CMOS technology.