Eero Ristolainen

System design issues for 3D system-in-package (SiP)

Development in electronics is driven by device and market needs. This paper focuses on system design issues for three-dimensional packaging technology and discusses interconnection density, material compatibility, thermal management, electrical requirements, related to delay and noise. Microelectronics packaging has to provide all future devices, such as electronics, actuators, sensors, antennas, optical/photonic, MEMS, and biological solutions. However, a 3D package is a cost effective solution to save placement and routing area on board using several IC processes in the same module. System-in-package (SiP) can combine all the electronic requirements of a functional system or a subsystem in one package. The driving force is integration without compromising individual chip technologies. In this work, a stacked system-in-package structure has been studied. The thermo-mechanical behavior of packages has been analyzed by finite element analysis (FEA) and the correlation between the experimental test results and the modeling was analyzed. A stacked 3D package can contain multiple heat sources that produce high power density. Therefore, thermal management needs extra attention to ensure safe operating temperatures under all conditions. The thermal behavior of the package was modeled using FEA and a boundary condition independent (BCI) compact thermal model (CTM) was built based on simulation results. In addition, high-speed signal and interfering environment set quite stringent requirements for 3D devices. Crosstalk between vertical connections was simulated and measured. Measurements of S-parameters were done using a network analyzer. The frequency range was 45 MHz to 20 GHz.

Study of adhesive flip chip bonding process and failure mechanisms of ACA joints

Abstract The flip chip bonding process using anisotropic conductive adhesives (ACA) and the consequent joint reliability were studied. The substrates used were rigid FR-4 boards, which are interesting due to their low cost and wide range of applications. The problems associated with the technique are discussed in this paper from the reliability point of view. Also, some aspects concerning production are introduced. The reliability of the joints was studied by accelerated environmental tests. A temperature cycling test was performed between temperatures −40 and +125 °C. Constant humidity testing was conducted at 85 °C and RH85%. In addition, reflow aging tests were performed using a conventional Sn/Pb reflow profile. For reducing the bonding cycle time, a two-stage curing process was used, which also utilizes the reflow process. The results show that the three bonding parameters, temperature, time, and pressure, all affect joint reliability. Most detrimental, however, seems to be reflow treatment performed after bonding. Most failures occurred only very briefly during the temperature cycling at the moment the temperature changed, while the joints were still conducting at both temperature extremes. However, a different failure mechanism caused a different kind of behavior during temperature cycling. The relationship between the failure modes and the failure mechanisms was studied using a scanning electron microscopy.

The effect of solder paste composition on the reliability of SnAgCu joints

Abstract As the electronics industry is moving towards lead-free manufacturing processes, more effort has been put into the reliability study of lead-free solder materials. Various tin–silver–copper-based solders have become widely accepted alternatives for tin–lead solders. In this study, we have tested three different SnAgCu solder compositions. The first consisted of a hypoeutectic 96.5Sn/3.0Ag/0.5Cu solder, the second of a eutectic 95.5Sn/3.8Ag/0.7Cu solder, and the third of a hypereutectic 95.5Sn/4.0Ag/0.5Cu solder. A eutectic SnPb solder was used as a reference. The test boards were temperature-cycled (−40 to +125 °C) until all samples failed. The results of the temperature cycling test were analyzed, and cross-section samples were made of the failed joints. Scanning electron and optical microscopy were employed to analyze the fracture behavior and microstructures of the solder joints. The reliability of lead-free solders and the effect of microstructures on joint reliability are discussed.

Stacked modular package

This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is a cost-effective solution to save placement and routing area on the board. Furthermore, a vertical module enables the benefit of several IC processes in the same module. The goal was to develop a method to produce a stacked modular package on a small scale, and to verify the feasibility of the solution. The main focus has been to test the bare die connections to the interposer and the vertical connections between interposers. The structure enables also, e.g., thin discretes, and passive arrays to be assembled on the interposer, thus enabling system-in-package (SiP) solutions. The method has been tested using thin daisy chain dice and daisy chain vertical interconnections. The dimensions of the developed six chip modules were 14/spl times/8/spl times/0.8-1 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were either 100 or 150-/spl mu/m thick, and the chips were thinned down to 90 /spl mu/s. Eutectic tin-lead solder bumps were used to mount the flip chips to the interposer. Solder-coated polymer spheres were used to stack the interposers on top of each other. The developed stacking process and vertical area interconnections by plastic core balls give good reliability and uniform stand-off height. Thermal cycling test +125/-40/spl deg/C until 2000 cycles proved reliability of the structure. Flip-chip failures were found after 500 cycles and only 1 of 32 vertical connection failures occurred during the test. Furthermore, this was caused, at least partly, by excess solder. Plastic ball as interconnection media between stacked layers gives good reliability and uniform stand-off height.

Thermal conduction at the nanoscale in some metals by MD

Abstract Miniaturization of electronic devices leads to nanoscale structures in the near future. As the system size decreases the heat dissipation density increases rapidly and the heat conduction becomes an important problem. Moreover, in very small systems the conduction is a size dependent phenomenon—conductivity decreases as the size decreases. We study the thermal conduction by phonons and its size dependency in seven metals, most of which are important in electronics. We use the molecular dynamic method with embedded atom potentials.

Reliability of 80 μm pitch flip chip attachment on flex

Abstract The interest toward flip chip technology has increased rapidly during last decade. Compared to the traditional packages and assembly technologies flip chip has several benefits, like less parasitics, the small package size and the weight. These properties emphasize especially when flip chip component is mounted direct to the flexible printed board. In this paper flip chip components with Kelvin four point probe and daisy chain test structure were bonded to the polyimide flex with two different types of anisotropically conductive adhesive films and one anisotropically conductive adhesive paste. The reliability of small pitch flip chip on flex interconnections (pitch 80 μm) was tested in 85°C/85% RH environmental test and −40↔+125°C thermal shock test. According to the results it is possible to achieve reliable and stable ohmic contact, even in small pitch flip chip on flex applications.

The influence of multiple reflow cycles on solder joint voids for lead‐free PBGAs

Lead‐free soldering is becoming a common practice in the electronics industry because of the growing general opposition to lead‐containing solders. The reliability of lead‐free solders has been studied a lot recently, but knowledge of it is still incomplete and many issues related to them are under heavy debate. This paper presents results from a study of the formation of voids with regard to the number of reflow cycles in three different kinds of solder joints: first the ones prepared with lead‐free solder paste and lead‐free plastic ball grid array (PBGA) components, next the ones prepared with lead‐free solder paste and tin‐lead‐silver PBGA components, and last the ones prepared with tin‐lead solder paste and tin‐lead‐silver PBGA components.

Effect of reflow profile on wetting and intermetallic formation between Sn/Ag/Cu solder components and printed circuit boards

The wetting performance and intermetallic formation of a Sn/Ag/Cu alloy on printed circuit board (PCB) surfaces and on component terminations were studied in this work. Two different PCB surface finishes, immersion gold over electroless nickel (Ni/Au) and an organic solderability preservative (OSP), were studied. Chip components with Sn/Pb coating and a gull‐wing type component with 100% Sn coating were used in these experiments. Different reflow profiles were tested, and the dependence of the wetting performance, intermetallic layer thickness and the microstructure of the solder joints on the reflow profile were investigated.It was found that reflow process conditions did not significantly influence the spreading or intermetallic formation on either of the surfaces. Neither the wetting onto the component nor the general microstructure of the solder joints varied significantly with the reflow profile. When a Sn/Pb ‐coated component was used, the content and size of Pb‐rich phases in the solder joint increased with a longer time above liquidus or a higher reflow peak temperature.

Stacked thin dice packaging

This paper reports on a developed stacking method to produce a small volume three-dimensional package. The first part of the 3/sup rd/ dimension is tackled by reducing package thickness and also the stand-off height. The steps came through thinning dice, using a thin interposer, and to stack the components. The thickness of the used ICs was 90 /spl mu/m, whereas typically thicknesses are around 250-300 /spl mu/m. Thin dice were connected through eutectic solder bumps on thin aramid epoxy substrates. The package was studied with the finite element method (FEM) using three-dimensional (3-D) models and the Ansys program. The average plastic work in the solder bump was used to define the reliability of the structure. Structures with one to four layers are compared. In current flip-chip assemblies, rigidity assists good electrical performance and reliability. Reducing the IC thickness below 100 /spl mu/m creates new challenges for handling, interconnecting, reliability and design. These tasks have been addressed in this study. The designed circuits for the above tests have been characterized and more details of the results are presented. Further progress in density increase has been achieved by stacking layers of flexible substrate and thin die on top of each other. For this work, the first level connection has been flip-chip bonding. The goal was to develop a method to produce modules on a small scale to verify the feasibility of various System-in-Package (SiP) solutions. The method has been tested using thin dice, mainly daisy chain. Devices are miniaturized to be more comfortable to carry; this size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Size reduction of electronics has set a challenge for packaging and provided the motivation to verify emerging technologies.

Solder bump reliability-issues on bump layout

The reliability of solder bumps in a typical under-filled flip chip package is calculated three-dimensionally (3-D) using the finite element method and a viscoplastic material model for the solder. Simulations are performed with varying bump placement, underfill coverage and board size. The average plastic work in a bump is used to compare the loading and bump reliability of different geometries. The results show possible improvements over the traditional bump placement by changing the geometry of the interconnects on the flip chip package. Three changes that improve reliability are discussed in detail: the redistribution of bump rows, the reduction of board size and the inclusion of heat transfer bumps.