Efstratios Kehayas

IST-LASAGNE: towards all-optical label swapping employing optical logic gates and optical flip-flops

The Information Society Technologies-all-optical LAbel SwApping employing optical logic Gates in NEtwork nodes (IST-LASAGNE) project aims at designing and implementing the first, modular, scalable, and truly all-optical photonic router capable of operating at 40 Gb/s. The results of the first project year are presented in this paper, with emphasis on the implementation of network node functionalities employing optical logic gates and optical flip-flops, as well as the definition of the network architecture and migration scenarios.

10-Gb/s all-optical half-adder with interferometric SOA gates

In this letter, we report an all-optical module that generates simultaneously four Boolean operations at 10 Gb/s. The circuit employs two cascaded ultrafast nonlinear interferometers and requires only two signals as inputs. The first gate is configured as a 2 /spl times/ 2 exchange-bypass switch and provides OR and AND logical operations. The second gate generates XOR (SUM bit) and AND (CARRY bit) Boolean operations and constitutes a binary half-adder. Successful operation of the system is demonstrated with 10-Gb/s return-to-zero pseudorandom data patterns.

All-optical network subsystems using integrated SOA-based optical gates and flip-flops for label-swapped networks

In this letter, we demonstrate that all-optical network subsystems, offering intelligence in the optical layer, can be constructed by functional integration of integrated all-optical logic gates and flip-flops. In this context, we show 10-Gb/s all-optical 2-bit label address recognition by interconnecting two optical gates that perform xor operation on incoming optical labels. We also demonstrate 40-Gb/s all-optical wavelength-switching through an optically controlled wavelength converter, consisting of an integrated flip-flop prototype device driven by an integrated optical gate. The system-level advantages of these all-optical subsystems combined with their realization with compact integrated devices, suggest that they are strong candidates for future packet/label switched optical networks

Rate multiplication by double-passing fabry-Perot filtering

We present a new technique for extending the decay time of the impulse response function of a Fabry-Perot filter while simultaneously maintaining a large bandwidth. It involves double passing through the filter and it can be used for the easy multiplication of the repetition rate of optical sources. We apply the concept to a 10-GHz pulse train to demonstrate experimentally the rate quadruplication to 40 GHz.

40-Gb/s All-Optical Processing Systems Using Hybrid Photonic Integration Technology

This paper presents an experimental performance characterization of all-optical subsystems at 40 Gb/s using interconnected hybrid integrated all-optical semiconductor optical amplifier (SOA) Mach-Zehnder interferometer (MZI) gates and flip-flop prototypes. It was shown that optical gates can be treated as generic switching elements and, when efficiently interconnected, can form larger and more functional network subsystems. Specifically, this paper reports on all-optical subsystems capable of performing on-the-fly packet clock recovery, 3R regeneration, label/payload separation, and packet routing using the wavelength domain. The all-optical subsystems are capable of operating with packet-mode traffic and are suitable for all-optical label-switched and self-routed network nodes. The intelligent functionality offered, combined with the compactness and stability of the optical gates, verifies the potential that all-optical technology can find application in future data-centric networks with efficient and dynamic bandwidth utilization. This paper also reports on the latest photonic integration breakthroughs as a potential migration path for reducing fabrication cost by developing photonic systems-on-chip utilizing multiple SOA-MZI optical gates on a single chip

Clock and data recovery circuit for 10-Gb/s asynchronous optical packets

We demonstrate an all-optical clock and data recovery circuit for short asynchronous data packets at 10-Gb/s line rate. The technique employs a Fabry-Perot filter and a SOA-based ultrafast nonlinear interferometer (UNI) to generate the local packet clock, followed by a second UNI gate to act as decision element, performing a logical AND operation between the extracted clocks and the incoming data packets. The circuit can handle short packets arriving at time intervals as short as 1.5 ns and arbitrary phase alignment.

Enabling Tb/s Photonic Routing: Development of Advanced Hybrid Integrated Photonic Devices to Realize High-Speed, All-Optical Packet Switching

We present recent advances in photonic integration introduced by integration-related European research project IST-MUFINS. The contribution of the project in the progress of a functional photonic integration is outlined, from device fabrication to device application focusing on photonic routing using multielement photonic chips. Specifically, we report on the transition from single-element to multielement photonic devices with the fabrication of hybrid integrated arrays of optical switches exploiting and upgrading the silica-on-silicon hybrid photonic integration. We demonstrate how the enhanced processing power and capacity of these components can be exploited to implement key functionalities required in next-generation fully integrated terabits per second photonic routers.

40 Gb/s all-optical packet clock recovery with ultrafast lock-in time and low inter-packet guardbands

We demonstrate a 40 Gb/s self-synchronizing, all-optical packet clock recovery circuit designed for efficient packet-mode traffic. The circuit locks instantaneously and enables sub-nanosecond packet spacing due to thelow clock persistence time. A low-Q Fabry-Perot filter is used as a passive resonator tuned to the line-rate that generates a retimed clock-resembling signal. As a reshaping element, an optical power-limiting gate is incorporated to perform bitwise pulse equalization. Using two preamble bits, the clock is captured instantly and persists for the duration of the data packet increased by 16 bits. The performance of the circuit suggests its suitability for future all-optical packet-switched networks with reduced transmission overhead and fine network granularity.

ARTEMIS: 40-gb/s all-optical self-routing node and network architecture employing asynchronous bit and packet-level optical signal processing

A 40-Gb/s asynchronous self-routing network and node architecture that exploits bit and packet level optical signal processing to perform synchronization, forwarding, and switching in the optical domain is presented. Optical packets are self-routed on a hop-by-hop basis through the network by using stacked optical tags, each representing a specific optical node. Each tag contains necessary control signals for configuring the node-switching matrix and forwarding each packet to the appropriate outgoing link and onto the next hop. In order to investigate the feasibility of their approach physical-layer simulations are performed, modeling each optical subsystem of the node showing acceptable signal quality and end-to-end bit error rates. In the All-optical self-RouTer EMploying bIt and packet-level procesSing (ARTEMIS) control plane, a timed/delayed resource reservation-based signaling scheme is employed combined with a load-balancing feedback-based contention-avoidance mechanism that can guarantee a high performance in terms of blocking probability and end-to-end delay

Pulse repetition frequency multiplication with spectral selection in Fabry-Perot filters

We present methods for obtaining high-repetition-rate full duty-cycle RZ optical pulse trains from lower rate laser sources. These methods exploit the memory properties of the Fabry-Perot filter for rate multiplication, while amplitude equalization in the output pulse train is achieved with a semiconductor optical amplifier or with a second transit through the Fabry-Perot filter. We apply these concepts to experimentally demonstrate rate quadruplication from 10 to 40 GHz and discuss the possibility of taking advantage of the proposed methods to achieve repetition rates up to 160 GHz.