Egbert G. T. Jaspers

Mapping of MPEG-4 decoding on a flexible architecture platform

In the field of consumer electronics, the advent of new features such as Internet, games, video conferencing, and mobile communication has triggered the convergence of television and computers technologies. This requires a generic media-processing platform that enables simultaneous execution of very diverse tasks such as high-throughput stream-oriented data processing and highly data-dependent irregular processing with complex control flows. As a representative application, this paper presents the mapping of a Main Visual profile MPEG-4 for High-Definition (HD) video onto a flexible architecture platform. A stepwise approach is taken, going from the decoder application toward an implementation proposal. First, the application is decomposed into separate tasks with self-contained functionality, clear interfaces, and distinct characteristics. Next, a hardware-software partitioning is derived by analyzing the characteristics of each task such as the amount of inherent parallelism, the throughput requirements, the complexity of control processing, and the reuse potential over different applications and different systems. Finally, a feasible implementation is proposed that includes amongst others a very-long-instruction-word (VLIW) media processor, one or more RISC processors, and some dedicated processors. The mapping study of the MPEG-4 decoder proves the flexibility and extensibility of the media-processing platform. This platform enables an effective HW/SW co-design yielding a high performance density.

Chip-set for video display of multimedia information

This paper presents a chip-set for digital video processing in a consumer television receiver. A key aspect of the chip-set is a high flexibility and programmability of multi-window features with multiple teletext pages, Internet pages and up to three live video windows. The chip-set consists of a microcontroller featuring pixel-based graphics, and a video processor containing a number of flexible co-processors for horizontal and vertical scaling, sharpness enhancement, adaptive temporal noise reduction, blending of graphics, mixing of multiple video streams and 100 Hz up-conversion.

A Flexible Heterogeneous Video Processor System For Television Applications.

A new video processing architecture for high-end TV applications is presented, featuring a flexible heterogeneous multi-processor architecture, executing video tasks in parallel and independently. The signal flow graph and the processors are programmable, enabling an optimal picture quality for different TV display modes. The concept is verified by an experimental chip design. The architecture allows several video streams to be processed and displayed in parallel and in a programmable way, with an individual signal quality.

Bandwidth reduction for video processing in consumer systems

The architecture of the present video processing units in consumer systems is usually based on various forms of processor hardware, communicating with an off-chip SDRAM memory. Examples of these systems are currently available MPEG encoders and decoders, and high-end television systems. Due to the fast increase of required computational power of consumer systems, the data communication to and from the off-chip memory has become the bottleneck in the overall system performance (memory wall problem). This paper presents a strategy for mapping pixels into the memory for video applications such as MPEG processing, thereby minimizing the transfer overhead between memory and the processing. A novelty in our approach is that the proposed communication model considers the statistics of the application-dependent data accesses in memory. With this technique, a 26% reduction of the memory bandwidth was obtained in an MPEG decoding system containing a 64-bit wide memory bus. For double-data-rate SDRAM (DDR SDRAM), the proposed mapping strategy reduces the bandwidth in the system by even 50%. This substantial performance improvement can readily be used for extending the quality or the functionality of the system.

Mapping of H.264 decoding on a multiprocessor architecture

Due to the increasing significance of development costs in the competitive domain of high-volume consumer electronics, generic solutions are required to enable reuse of the design effort and to increase the potential market volume. As a result from this, Systems-on-Chip (SoCs) contain a growing amount of fully programmable media processing devices as opposed to application-specific systems, which offered the most attractive solutions due to a high performance density. The following motivates this trend. First, SoCs are increasingly dominated by their communication infrastructure and embedded memory, thereby making the cost of the functional units less significant. Moreover, the continuously growing design costs require generic solutions that can be applied over a broad product range. Hence, powerful programmable SoCs are becoming increasingly attractive. However, to enable power-efficient designs, that are also scalable over the advancing VLSI technology, parallelism should be fully exploited. Both task-level and instruction-level parallelism can be provided by means of e.g. a VLIW multiprocessor architecture. To provide the above-mentioned scalability, we propose to partition the data over the processors, instead of traditional functional partitioning. An advantage of this approach is the inherent locality of data, which is extremely important for communication-efficient software implementations. Consequently, a software implementation is discussed, enabling e.g. SD resolution H.264 decoding with a two-processor architecture, whereas High-Definition (HD) decoding can be achieved with an eight-processor system, executing the same software. Experimental results show that the data communication considerably reduces up to 65% directly improving the overall performance. Apart from considerable improvement in memory bandwidth, this novel concept of partitioning offers a natural approach for optimally balancing the load of all processors, thereby further improving the overall speedup.

Architecture of embedded video processing in a multimedia chip-set

A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-window features with, for example, full-motion video, Internet and Teletext. To provide a large amount of computational power for such a full-featured application domain and to prevent the system from a communication bottleneck to the external memory, a heterogenous multi-processor architecture is implemented. The architecture offers a minimum of external communication overhead and enables programming on high functional level. The chip-set can simultaneously display e.g. two full-motion video windows, an Internet page and an additional mail indicator in front of a pixel-based wallpaper background. In addition, the video can be noise reduced and enhanced in sharpness together with a 50-100 Hz conversion to reduce field flicker.

On the design of multimedia software and future system architectures

A principal challenge for reducing the cost for designing complex systems-on-chip is to pursue more generic systems for a broad range of products. For this purpose, we explore three new architectural concepts for state-of-art video applications. First, we discuss a reusable scalable hardware architecture employing a hierarchical communication network fitting with the natural hierarchy of the application. In a case study, we show that MPEG streaming in DTV occurs at high level, while subsystems communicate at lower levels. The second concept is a software design that scales over a number of processors to enable reuse over a range of VLSI process technologies. We explore this via an H.264 decoder implementation scaling nearly linearly over up to eight processors by applying data partitioning. The third topic is resource-scalability, which is required to satisfy realtime constraints in a system with a high amount of shared resources. An example complexity-scalable MPEG-2 coder scales the required cycle budget with a factor of three, in parallel with a smooth degradation of quality.

System-level analysis for MPEG-4 decoding on a multi-processor architecture

The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging from stream-oriented processing to highly data-dependent irregular processing with complex control. This paper presents the mapping of a Main-Visual profile MPEG-4 decoder for High-Definition (HD) video onto a flexible architecture platform. The hardware-software (HWSW) design is derived by analyzing a partitioning of distinct tasks within the application. The proposed implementation contains a hierarchy of processors, which are matched to the characteristics of the processing tasks. Additionally, we introduce a hierarchy in communication and memory for memory-bandwidth efficiency and flexibility for HW reuse. The architecture provides various trade-off possibilities (flexibility, extensibility, HW-SW) while achieving the high performance density (i.e. the performance per unit area per unit power) that is required for consumer systems.

Compression for reduction of off-chip video bandwidth

The architecture for block-based video applications (e.g. MPEG/JPEG coding, graphics rendering) is usually based on a processor engine, connected to an external background SDRAM memory where reference images and data are stored. In this paper, we reduce the required memory bandwidth for MPEG coding up to 67% by identifying the optimal block configuration and applying embedded data compression up to a factor four. It is shown that independent compression of fixed-sized data blocks with a fixed compression ratio can decrease the memory bandwidth for a limited set of compression factors only. To achieve this result, we exploit the statistical properties of the burst-oriented data exchange to memory. It has been found that embedded compression is particularly attractive for bandwidth reduction when a compression ratio 2 or 4 is chosen. This moderate compression factor can be obtained with a low-cost compression scheme such as DPCM with a small acceptable loss of quality.

Synchronization of video in distributed computing systems

A distributed multimedia computing system consists of sources, processing units and presentation devices in which each component operates autonomously. This independency can be exploited for optimization of individual component performance. Flexibility in performance improvement is enhanced by using independent clock domains. This paper presents a Video I/O model for such a multimedia system. This model provides an asynchronous communication interface for independent clock domains with the ability to synchronize a video display to one of the video sources. The communication interface has been used for the design of I/O modules in a multimedia system, which are briefly outlined.