Ehrenfried Seebacher

Interface traps density-of-states as a vital component for hot-carrier degradation modeling

We refine our approach for hot-carrier degradation modeling based on a thorough evaluation of the carrier energy distribution by means of a full-band Monte–Carlo simulator. The model is extended to describe the linear current degradation over a wide range of operation conditions. For this purpose we employ two types of interface states, either created by single- or by multiple-electron processes. These traps apparently have different densities of states which is important to consider when calculating the charges stored in these traps. By calibrating the model to represent the degradation of the transfer characteristics, we extract the number of particles trapped by both types of interface traps. We find that traps created by the single- and multiple-electron mechanisms are differently distributed over energy with the latter shifted toward higher energies. This concept allows for an accurate representation of the degradation of the transistor transfer characteristics.

MOS varactor modeling with a subcircuit utilizing the BSIM3v3 model

This paper presents a subcircuit model for an MOS varactor based on the BSIM3v3 model suitable for simulator implementation within circuit-design environments. The development of the model and BSIM3v3 model parameter settings are discussed in detail. By varying the length (L) of the device, C/sub MAX//C/sub MIN/ ratios as high as five or minimum quality factors of 21.5 at 2.4 GHz can be achieved using a standard 0.35 /spl mu/m CMOS process. The investigation of different geometries resulted in a tradeoff between capacitance tuning and quality factor. A medium length varactor has been characterized.

A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal-oxide-semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just as that of a low-voltage inner MOS transistor. It exploits the charge-sheet approximation and performs linearization between the charge in the drift region and the surface potential. The drift region model combined with the standard charge-sheet MOS model for the low-voltage part adds up to a complete HV-MOSFET model, which is verified against technology computer-aided design simulations and measurements of HV-MOS transistors. The comparisons demonstrate its accurate physics foundations and underline that this novel approach to the modeling of the drift region of the HV-MOSFET is promising.

Hot-carrier degradation modeling using full-band Monte-Carlo simulations

We propose and verify a model for hot carrier degradation based on the exhaustive evaluation of the energy distribution function for charge carriers in the channel by means of a full-band Monte-Carlo device simulator. This approach allows us to capture the interplay between “hot” and “colder” electrons and their contribution to the damage build-up. In fact, particles characterized by higher energy are able to produce interface traps by a single-carrier process while colder ones trigger multivibrational mode excitation of a Si-H bond. For the model validation we use long-channel MOSFETs and represent the degradation of the linear drain current. The single-carrier component dominates degradation (this is the usual tendency for long devices), however, the multiple-carrier process is still considerable being less and less pronounced as the source-drain stress voltage increases

SPICE modeling of process variation using location depth corner models

For robust designs, the influence of process variations has to be considered during circuit simulation. We propose a nonparametric statistical method to find sets of simulation parameters that cover the process spread with a minimum number of simulation runs. Process corners are determined from e-test parameter vectors using a location depth algorithm. The e-test corner vectors are then transformed to SPICE parameter vectors by a linear mapping. A special corner extension algorithm makes the resulting simulation setup robust against moderate process shifts while preserving the underlying correlation structure. To be applicable in a production and circuit design environment, the models are integrated into an automated model generation flow for usage within a design-framework. The statistical methods are validated for analog/mixed-signal benchmark circuits.

Investigations on the high current behavior of lateral diffused high-voltage transistors

This paper describes the high current behavior of a lateral, n-channel, high-voltage transistor. The starting points are TCAD experiments where the phenomenological behavior is analyzed. Based on these results a transistor high current model is derived, which is based on the vertical integrated free carrier concentration in the drift region. The important model parameter is the gate voltage, which defines the boundary condition for the free electron concentration at the beginning of the drift region. Because of the coupling of the carrier continuity equation and the Poisson equation (drift-diffusion model), this boundary condition plays a major role, and defines the carrier concentration inside the drift region. Together with an intrinsic low-voltage transistor model (intrinsic NMOS transistor), a series network is solved numerically. The network behavior reflects the TCAD experiments quite well and covers the different electrical regimes (the on-resistance regime, the quasi-saturation regime, and the saturation regime). The model output is compared with the TCAD experiments and the measured transistor data as well.

Domain Partitioning Based Parametric Models for Passive On-Chip Components

This paper shows how to obtain models for passive integrated components that take into consideration the variability inherent to their design. To achieve this, the computational domain is split into sub-domains in which the electromagnetic circuit element (EMCE) formulation is used. The variability is described by using first order Taylor Series representation for the semi-state space matrices. The novelty of the paper is that it describes how the EMCE based parametric models can be obtained. The parametric sub-models can be interconnected afterwards to obtain a global parametric model that can be simulated or reduced. The advantage of this approach is that it bears an inherent parallelism. The sub-models can be treated independently both from the point of view of the variability, and from the point of view of electromagnetic field formulation. Both aspects are illustrated with a simple test case as well as a real benchmark designed and characterized at austriamicrosystems.

High-Voltage MOSFET Modeling

In many new applications like communication and automotive electronics the usage of integrated high voltage MOS transistors (LDMOS and DMOS) requires highly accurate compact models. In this chapter we present a deep look into special LDMOS transistor behavior and discuss state of the art sub-circuit modeling with BSIM/EKV core and JFET/Resistor approach. Parasitic diode and bipolar effects are discussed and modeling suggestions are presented. The EKV high voltage model developed by Swiss Federal Institute of Technology (EPFL) and the MM20 high voltage model introduced by NXP Research (formerly Philips Research) Laboratories is demonstrated in detail. The first CMC (Compact Modeling Council) standard high voltage MOSFET model HiSIM_HV developed by Hiroshima University is explained as well. Finally, characterization and measurement strategies for LDMOS modeling are described.

An analytical approach for physical modeling of hot-carrier induced degradation

We develop an analytical model for hot-carrier degradation based on a rigorous physics-based TCAD model. The model employs an analytical approximation of the carrier acceleration integral (calculated with our TCAD approach) by a fitting formula. The essential features of hot-carrier degradation such as the interplay between single-and multiple-electron components of Si–H bond dissociation, mobility degradation during interface state build-up, as well as saturation of degradation at long stress times are inherited. As a result, the change of the linear drain current can be represented by the analytical expression over a wide range of stress conditions. The analytical model can be used to study the impact of device geometric parameters on hot-carrier degradation.

Measurement and Compact Modeling of 1/f Noise in HV-MOSFETs

This paper investigates 1/f noise behavior under low and high drain biases of high-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) (HV-MOSFETs). A dedicated setup is presented which allows measuring low-frequency (LF) noise of lateral double-diffused MOSFETs (LDMOSFETs) up to 200 V at the drain. LF noise spectra of n- and p-channel LDMOSFETs were measured over a large range of gate and drain bias conditions and modeled using a recently established physics-based compact model of HV-MOSFETs. The investigated devices confirm that the overall noise is mostly dominated by the noise originating in the channel, while the drift-region-generated noise only is apparent in linear operation.