Eiji Ogura

A 1.2 W single-chip MPEG2 MP@ML video encoder LSI including wide search range motion estimation and 81 MOPS controller

Most conventional MPEG2 video encoder chip-sets use full-search block-matching algorithms (FSMBA) for motion estimation requiring large computation power and complex hardware. Thus, reducing the amount of motion-estimation hardware is key to designing a practical, cost-effective single-chip encoder. Two algorithms for adaptive motion estimation are implemented to achieve wide search area with less hardware than required by FSBMA. Using an efficient pipeline architecture and optimizing circuitry and data transfers with the external memory results in reduced external memory requirements and low power consumption.

A 1.2-W single-chip MPEG2 MP@ML video encoder LSI including wide search range (H/spl plusmn/288, V:/spl plusmn/96) motion estimation and 81-MOPS controller

An MPEG2 MP@ML video encoder large-scale integrated circuit (LSI) has been developed including an 81 MOPS controller and motion estimator. By using two adaptive algorithms, a wide motion-estimation search area (/spl plusmn/288 pixels horizontal and /spl plusmn/96 pixels vertical) was achieved with computation complexity of only 0.5% (20 GOPS) of full search block-matching algorithm. By using this expanded motion-estimation search area, there is a significant improvement in picture quality for coding fast motion sequences. The power consumption was reduced by using an efficient pipeline architecture and optimizing the circuitry, especially in the motion-estimation block and the data transfers for the external SDRAM. The 13.7/spl times/12.4 mm/sup 2/, 4.5-M transistor device using 0.4-/spl mu/m CMOS technology dissipates 1.2 W at 3.3 V.