Eiji Tamura

Path Delay Analysis for Hierarchical Building Block Layout System

This paper describes a path delay analysis system which employs an accurate signal delay calculation method for MOS LSIs, taking poly resistance into account. The system takes mask patterns generated by a hierarchical building block layout system as inputs, and verifies timing margins of a large scale random logic LSI in a module-wise bottom up fashion. Path delay analysis using a critical path trace algorithm and an enumerative path trace algorithm in combination is effective in locating critical timing regions in a chip and in analyzing critical paths in the regions in detail.

Path delay analysis for hierarchical building block layout systems

This paper describes a path delay analysis system which employs an accurate signal delay calculation method for MOS LSIs, taking poly resistance into account. The system takes mask patterns generated by a hierarchical building block layout system as inputs, and verifies timing margins of a large scale random logic LSI in a module-wise bottom up fashion. Path delay analysis using a critical path trace algorithm and an enumerative path trace algorithm in combination is effective in locating critical timing regions in a chip and in analyzing critical paths in the regions in detail.