Einar J. Aas

Quantifying design quality: a model and design experiments

A design process model, focusing on design quality, is presented. Design quality is quantified as the probability that a design object satisfies its specification. Simple economic models demonstrate how design quality may impact cost, revenue, and lead time. Finally, design experiments done by several students are reported to exemplify the collection of design process parameters. These experiments also demonstrate the applicability of such parameters and quality models to real-life design projects.<<ETX>>

Quantifying design quality through design experiments

The authors present a model for design quality metrics, discuss its relevance, and give some examples of use. Design experiments demonstrate error data extraction and analysis. Using a model of the design process for electronic products that emphasizes the resulting quality of the design, the authors demonstrated that they can quantify design quality. They can best express the probability of an error-free design in terms of the quality of the synthesis process and the quality of the verification procedure.<<ETX>>

State transition graph analysis as a key to BIST fault coverage

The authors consider the analysis of the state transition graph (STG) as a key to understanding the state and fault coverage of BIST (built-in self-test) schemes. Some interesting topological properties of STGs are found. These may be exploited when BIST schemes are being designed. Specifically, the problem of limit cycles in STGs is discussed, and ways of defining initial states to yield long paths before state repetition are presented. One BIST scheme that has modest overhead requirements and is based on serial shift registers is given. The scheme is applied to some of the ISCAS-89 benchmark circuits, and experimental results on fault coverage are presented.<<ETX>>

Monte Carlo calculation of the electron drift velocity in GaAs with a superlattice

Monte Carlo calculations of the drift velocity and mean energy vs electric field in n‐type GaAs with a superlattice are reported. The model allows for phonon scattering, and a simple sinusoidal band shape in the direction of the superlattice is assumed. Negative differential mobility and energy saturation appear, and their variation with lattice temperature and miniband width is discussed. The threshold field decreases and the absolute value of the differential mobility increases with decreasing lattice temperature, while the miniband width has minor influence on these parameters. Schockley streaming is observed at low lattice temperature.

Comparison of two architectures for implementation of the discrete cosine transform

A new DCT architecture developed by Mou and Jutand (1991) is compared to an architecture based on distributed arithmetic with ROMs realized as random logic. Both architectures have been implemented in 0.8 /spl mu/m CMOS technology and optimized with different constraints on area and timing. The results reveal that for HDTV applications the design with distributed arithmetic is superior, with lower power consumption and less than half the chip area.

Experiments with autonomous test of PLAs

An architecture for BIST of PLAs is presented, together with a testability analysis tool to assert test quality. The functionality of the PLA itself is utilized for stimuli generation. Experiments assert that the test patterns generated can be considered as random patterns with equal 1 and 0 probability of each input. Test quality is measured based upon computed fault detectability and estimated fault coverage at a desired confidence level. A set of 53 PLA benchmark circuits from Berkeley is used to demonstrate the features of the method. It is found that 37 of 53 PLAs are random testable to 99% fault coverage with less than 100000 patterns.<<ETX>>